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    • 3. 发明授权
    • Digital clock or other counting device with resilient coupling means in the drive train
    • 数字时钟或具有传动系中弹性耦合装置的其他计数装置
    • US3918252A
    • 1975-11-11
    • US44874974
    • 1974-03-06
    • TRI TECH
    • HAYDON ARTHUR W
    • G04B19/21G04C19/04G06M1/04G06M1/14G04B19/02G04B19/00G06C15/26
    • G06M1/143G04B19/21G04C19/04G06M1/041
    • A digital clock or other counting device in which the output shaft on the drive motor of the device is resiliently connected to the gear train by means of a spiral spring. The drive motor is of the stepper motor type and applies energy to the spring in discrete increments. During the initial portion of each increment, the gear train remains stationary, and it then gradually accelerates and continues its movement after the motor shaft has come to rest. The arrangement is such that there is a very smooth and quiet transfer of energy from the shaft through the gear train to the individual counting elements. In some embodiments the counting elements comprise register drums in which motion is transferred between certain of the drums by a Geneva type transfer pinion assembly and between other drums by resiliently biased planetary gearing.
    • 数字时钟或其他计数装置,其中装置的驱动电动机上的输出轴通过螺旋弹簧弹性地连接到齿轮系。 驱动电机是步进电机类型,并以离散增量向弹簧施加能量。 在每个增量的初始部分期间,齿轮系保持静止,然后在电动机轴静止之后逐渐加速并继续其运动。 这种布置使得能量从轴通过齿轮系到各个计数元件非常平滑和安静地传递。 在一些实施例中,计数元件包括定位鼓,其中运动通过日内瓦型传递小齿轮组件在某些滚筒之间并且通过弹性偏置的行星齿轮传动在其它滚筒之间。
    • 4. 发明授权
    • Four-phase high speed counter
    • 四相高速计数器
    • US3654441A
    • 1972-04-04
    • US3654441D
    • 1970-11-16
    • RCA CORP
    • BHARALI UIPALANANDA
    • H03K23/00G06M1/14H03K23/08
    • H03K23/001
    • In response to each pulse to be counted, the bit stored in each stage of the counter is sensed. In the case of up-counting, when the j least significant bits are 1 and the j + 1th least significant bit is a 0, the stages storing these j + 1 bits are caused concurrently to change state, and where j is any integer which is less than n, and n is the number of stages in the counter. In the case of down-counting, the same procedure is followed for the complementary case. The counter may be implemented with metal oxide semiconductor (MOS) field-effect transistors.
    • 响应于要计数的每个脉冲,感测存储在计数器的每个级中的位。 在递增计数的情况下,当j个最低有效位为1并且j + 1个最低有效位为0时,存储这些j + 1位的级同时引起改变状态,并且其中j是任何整数, 小于n,n是计数器中的级数。 在下计数的情况下,补充案件遵循相同的程序。 计数器可以用金属氧化物半导体(MOS)场效应晶体管来实现。