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1. 发明授权

US3696389A Display system utilizing light emitting devices 失效
标题翻译：显示系统利用发光装置
公开(公告)号：US3696389A
公开(公告)日：1972-10-03
申请号：US3696389D
申请日：1970-07-20
申请人： GEN ELECTRIC
发明人： FENNER GUNTHER E
IPC分类号： G09G3/32 , H01L33/00 , H03K23/00 , H03K19/14 , G02F3/00
CPC分类号： H03K23/001 , G09G3/32 , G09G2300/0842 , G09G2300/088 , G09G2300/0885 , G09G2360/148 , H01L25/167 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for receiving, transferring, retaining and displaying information within a display system having inherent internal memory capabilities. Transfer and display elements including light-emitting and light-activated devices are employed in numerous configurations to provide display systems of high density with a minimum number of connections to external control circuitry with self-sustaining memory capabilities. Row-by-row, column-by-column and time sequential addressing of both rows and columns of display elements are disclosed.
摘要翻译：用于在具有固有内部存储器能力的显示系统内接收，传输，保留和显示信息的方法和装置。包括发光和光激活装置在内的传输和显示元件被用于许多配置，以提供具有最小数量的具有自维持存储器能力的外部控制电路的连接的高密度显示系统。公开了显示元素的行和列的逐行，逐列和时间顺序寻址。

2. 发明授权

US3654441A Four-phase high speed counter 失效
标题翻译：四相高速计数器
公开(公告)号：US3654441A
公开(公告)日：1972-04-04
申请号：US3654441D
申请日：1970-11-16
申请人： RCA CORP
发明人： BHARALI UIPALANANDA
IPC分类号： H03K23/00 , G06M1/14 , H03K23/08
CPC分类号： H03K23/001
摘要： In response to each pulse to be counted, the bit stored in each stage of the counter is sensed. In the case of up-counting, when the j least significant bits are 1 and the j + 1th least significant bit is a 0, the stages storing these j + 1 bits are caused concurrently to change state, and where j is any integer which is less than n, and n is the number of stages in the counter. In the case of down-counting, the same procedure is followed for the complementary case. The counter may be implemented with metal oxide semiconductor (MOS) field-effect transistors.
摘要翻译：响应于要计数的每个脉冲，感测存储在计数器的每个级中的位。在递增计数的情况下，当j个最低有效位为1并且j + 1个最低有效位为0时，存储这些j + 1位的级同时引起改变状态，并且其中j是任何整数，小于n，n是计数器中的级数。在下计数的情况下，补充案件遵循相同的程序。计数器可以用金属氧化物半导体（MOS）场效应晶体管来实现。

3. 发明授权

US3500342A Electrolytic cell counter 失效
标题翻译：电解池计数器
公开(公告)号：US3500342A
公开(公告)日：1970-03-10
申请号：US3500342D
申请日：1967-06-19
申请人： BISSETT BERMAN CORP
发明人： BISSETT THOMAS B , TATCH MARTIN S
IPC分类号： G01N3/06 , H03K23/00 , G11B31/00
CPC分类号： H03K23/001 , G01N3/066

4. 发明授权

US3567908A Drive circuits for solid state clock displays 失效
标题翻译：用于固态时钟显示的驱动电路
公开(公告)号：US3567908A
公开(公告)日：1971-03-02
申请号：US3567908D
申请日：1969-01-23
申请人： GEN TIME CORP
发明人： INGENITO MICHAEL J
IPC分类号： G04G9/06 , H03K23/00 , H05B3/10 , H01J39/12
CPC分类号： G04G9/06 , H03K23/001
摘要： The disclosed solid state clock drive circuit comprises cascaded ring counters, whose stages comprise at least one heater element and one thermistor. A bistable switch, in response to timing pulses, alternately connects alternate stages of each ring counter to a current source such that energizing current flows through only one stage of each ring counter. Thermal coupling between the heater element and thermistor of adjacent stages controls the transfer of energizing current flow from stage to stage upon operation of the switches. A material applied to each heater element produces a visual effect when heated, thus developing a time display.

5. 发明授权

US3564429A Programmable rate oscillator 失效
标题翻译：可编程速率振荡器
公开(公告)号：US3564429A
公开(公告)日：1971-02-16
申请号：US3564429D
申请日：1969-02-05
申请人： US NAVY
发明人： MILLER LAWRENCE , PADGETT CLARENCE W , RUHL WILEY T JR , SCHULTZ WALTER J
IPC分类号： H03K5/135 , H03K23/00 , H03K5/00
CPC分类号： H03K5/135 , H03K23/001
摘要： A PROGRAMMABLE RATE OSCILLATOR HAVING A METAL OXIDE SEMICONDUCTOR (MOS) RECIRCULATING SHIFT REGISTER TYPE COUNTER COUPLED TO A DIGITAL COMPARATOR TO WHICH IS ALSO COUPLED A PROGRAMMED DIGITAL INPUT TIME DELAY TO SWITCH A BISTABLE MULTIVIBRATOR AT THE BEGINNING OF EACH COUNT AND AGAIN AT THE DIGITAL EQUALITY OF THE PROGRAMMED DIGITAL INPUT WITH THE SHIFT REGISTER ACCUMULATION IN A DATA SAMPLED SEQUENCE TO PRODUCE A ONE-SHOT OUTPUT DELAY IN ACCORDANCE WITH THE PROGRAMMED INPUT TIME DELAY WITH MEANS CONNECTED IN ASSOCIATION THEREWITH TO INDICATE VALID AND INVALID DATA SAMPLES.

6. 发明授权

US2512679A Means for counting electrical impulses 失效
标题翻译：用于计算电脉冲的方法
公开(公告)号：US2512679A
公开(公告)日：1950-06-27
申请号：US70483946
申请日：1946-10-22
申请人： INT STANDARD ELECTRIC CORP
发明人： SYDNEY RIDLER DESMOND
IPC分类号： H03K21/00 , H03K23/00
CPC分类号： H03K21/00 , H03K23/001

7. 发明授权

US3766408A Counter using insulated gate field effect transistors 失效
标题翻译：使用绝缘栅场效应晶体管的计数器
公开(公告)号：US3766408A
公开(公告)日：1973-10-16
申请号：US3766408D
申请日：1972-05-03
申请人： TOKYO SHIBAURA ELECTRIC CO
发明人： SUZUKI Y , HIRASAWA M
IPC分类号： H03K3/038 , H03K23/00 , H03K23/44 , H03K27/00
CPC分类号： H03K3/038 , H03K23/001 , H03K23/44
摘要： An n-scale counter comprising first memory cells or shift registers cascade connected in a number of (n-2), one second memory cell or shift register and one inverter circuit. Each of the first memory cells has first and second input terminals and one output terminal. While an input signal to the second or reset terminal has a first voltage level, an input signal applied to the first input terminal is taken out as an output signal at the output terminal with a delay of a predetermined length of time, and while an input signal to the reset terminal has a second voltage level, an output signal from the output terminal is reset. The second memory cell has one input terminal and one output terminal so as to cause a signal supplied to input terminal to be taken out as an output signal at the output terminal with a delay of a predetermined length of time. The second memory cell and inverter are connected between the foremost and rearmost units of the first memory cell assembly, and the junction of the second memory cell and the inverter circuit is connected to the respective second input terminals of the first memory cells.
摘要翻译：一个n级计数器，包括在多个（n-2）个1秒存储单元或移位寄存器和一个反相器电路中串联的第一存储器单元或移位寄存器。每个第一存储单元具有第一和第二输入端和一个输出端。当向第二或复位端子的输入信号具有第一电压电平时，以预定时间长度的延迟在输出端子处取出施加到第一输入端子的输入信号作为输出信号，而在输入端对复位端子的信号具有第二电压电平，来自输出端子的输出信号被复位。第二存储单元具有一个输入端和一个输出端，以便以预定的时间长度的延迟使得提供给输入端的信号作为输出端被取出作为输出信号。第二存储单元和逆变器连接在第一存储单元组件的最前面和最后面的单元之间，第二存储单元和逆变器电路的结连接到第一存储单元的相应第二输入端。

8. 发明授权

US3657557A Synchronous binary counter 失效
标题翻译：同步二进制计数器
公开(公告)号：US3657557A
公开(公告)日：1972-04-18
申请号：US3657557D
申请日：1970-10-19
申请人： GEN INSTRUMENT CORP
发明人： SMITH KENT F , WANLASS FRANK M
IPC分类号： H03K23/00 , H03K23/22
CPC分类号： H03K23/001
摘要： A multistage synchronous binary counter has an improved high speed carry means which is responsive only to the previous stage. Each stage comprises three inverters connected in series, the first and second inverters being isolated periodically by a clocked switching device. Two feedback paths in each stage comprising two switching devices each are adapted to feed back the signals at the outputs of the second and third inverters respectively to the input node, the control terminals of said switching devices being connected to selected nodes in the preceding stage. Another clocked switching device is interposed in both feedback paths whereby each count takes place over a period defined by first and second nonoverlapping clock signals applied to the first and second clocked switching devices, respectively.
摘要翻译：多级同步二进制计数器具有改进的高速进位装置，其仅响应于前一级。每个级包括串联连接的三个反相器，第一和第二反相器被定时开关器件周期性隔离。包括两个开关装置的每个级中的两个反馈路径分别适于将第二和第三反相器的输出端的信号反馈到输入节点，所述开关装置的控制端在前一级连接到选定的节点。另一个时钟切换装置插入在两个反馈路径中，由此每个计数分别在由施加到第一和第二时钟控制的开关装置的第一和第二非重叠时钟信号限定的时段内进行。

9. 发明授权

US3457429A Electrothermal timing apparatus 失效
标题翻译：电热定时装置
公开(公告)号：US3457429A
公开(公告)日：1969-07-22
申请号：US3457429D
申请日：1967-01-09
申请人： FRANCIS P BUITING
发明人： BUITING FRANCIS P
IPC分类号： G04F5/00 , G04G3/02 , H01H43/30 , H03K23/00 , H02H3/00 , H01H7/06 , H02B1/24
CPC分类号： H01H43/308 , G04F5/00 , G04G3/02 , H03K23/001 , Y10T307/484 , Y10T307/773 , Y10T307/951

10. 发明授权

US3098159A Cryogenic ring circuit 失效
标题翻译：低温环路
公开(公告)号：US3098159A
公开(公告)日：1963-07-16
申请号：US70555357
申请日：1957-12-27
申请人： IBM
发明人： BRENNEMANN ANDREW E
IPC分类号： G06F1/04 , G11C19/32 , H03K21/00 , H03K23/00
CPC分类号： G11C19/32 , G06F1/04 , H03K21/00 , H03K23/001 , Y10S505/857

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