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1. 发明授权

US08164390B1 Regulating an operating condition of an integrated circuit to compensate for a manufacturing variation 有权
标题翻译：调节集成电路的工作状态以补偿制造变化
公开(公告)号：US08164390B1
公开(公告)日：2012-04-24
申请号：US12048957
申请日：2008-03-14
申请人： Randall D. Briggs , Eran Maor , Walter Lee McNall , William B. Weiser , Haggai Telem
发明人： Randall D. Briggs , Eran Maor , Walter Lee McNall , William B. Weiser , Haggai Telem
IPC分类号： H03L7/081
CPC分类号： H03L7/081
摘要： An integrated circuit has operational circuitry to perform an operation. An operational regulator regulates an operating condition of the operational circuitry. The operational regulator has a sample clock to generate a sample clock signal. The sample clock signal correlates to a manufacturing variation of the electronic circuitry. The operational regulator also includes a configurator to evaluate the sample clock signal and generate a configuration signal according to the evaluation. A controller is provided to receive the configuration signal and control an operating condition of the operational circuitry according to the configuration signal.
摘要翻译：集成电路具有执行操作的操作电路。操作调节器调节操作电路的工作状态。操作调节器具有采样时钟以产生采样时钟信号。采样时钟信号与电子电路的制造变化相关。操作调节器还包括用于评估采样时钟信号并根据评估产生配置信号的配置器。提供控制器以接收配置信号并根据配置信号控制操作电路的操作状态。

2. 发明授权

US08810589B1 Method and apparatus for refreshing display 有权
标题翻译：用于刷新显示的方法和装置
公开(公告)号：US08810589B1
公开(公告)日：2014-08-19
申请号：US12942178
申请日：2010-11-09
申请人： Rabeeh Khoury , Dan Ilan , Eran Maor
发明人： Rabeeh Khoury , Dan Ilan , Eran Maor
IPC分类号： G06F13/00 , G09G5/39
CPC分类号： G09G5/395 , G09G5/39 , G09G2330/021 , G09G2360/121 , G09G2360/125 , G09G2360/128 , G09G2380/14
摘要： Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first memory, a memory controller, and a display controller coupled to a display module. The memory controller is selectively coupled to the first memory and to a second memory that has higher power consumption than the first memory. The second memory includes a frame buffer storing pixel data of images to be displayed on the display module. When the integrated circuit enters a power saving mode, the memory controller, while coupled to the first memory and the second memory, pre-fetches pixel data of an image from the second memory into the first memory at a first data rate. Further, when the integrated circuit is in the power saving mode, the display controller streams the pixel data from the first memory to the display module at a second data rate that is lower than the first data rate, and the second memory is configured into a memory power-saving mode after the pre-fetching until the second memory is accessed for additional pixel data.
摘要翻译：本公开的方面提供集成电路。集成电路包括第一存储器，存储器控制器和耦合到显示模块的显示控制器。存储器控制器选择性地耦合到第一存储器和具有比第一存储器更高的功耗的第二存储器。第二存储器包括存储要在显示模块上显示的图像的像素数据的帧缓冲器。当集成电路进入省电模式时，存储器控制器在耦合到第一存储器和第二存储器的同时，以第一数据速率从第二存储器预取图像的像素数据到第一存储器。此外，当集成电路处于省电模式时，显示控制器以比第一数据速率低的第二数据速率将像素数据从第一存储器流向显示模块，并且将第二存储器配置为预取后的存储器省电模式，直到第二个存储器被访问为其他像素数据。

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