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1. 发明申请

US20070159911A1 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20070159911A1
公开(公告)日：2007-07-12
申请号：US11713284
申请日：2007-03-02
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C8/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列的矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

2. 发明授权

US07187581B2 Semiconductor memory device and method of operating same 有权
公开(公告)号：US07187581B2
公开(公告)日：2007-03-06
申请号：US11079590
申请日：2005-03-14
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

3. 发明申请

US20080205114A1 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20080205114A1
公开(公告)日：2008-08-28
申请号：US12082020
申请日：2008-04-08
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C5/06
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

4. 发明授权

US07359229B2 Semiconductor memory device and method of operating same 有权
公开(公告)号：US07359229B2
公开(公告)日：2008-04-15
申请号：US11713284
申请日：2007-03-02
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

5. 发明授权

US07085153B2 Semiconductor memory cell, array, architecture and device, and method of operating same 失效
标题翻译：半导体存储器单元，阵列，架构和器件及其操作方法
公开(公告)号：US07085153B2
公开(公告)日：2006-08-01
申请号：US10829877
申请日：2004-04-22
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/24
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“1”）。可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

6. 发明申请

US20050174873A1 Semiconductor memory device and method of operating same 有权
公开(公告)号：US20050174873A1
公开(公告)日：2005-08-11
申请号：US11096970
申请日：2005-04-01
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C20060101 , G11C8/00 , G11C11/00 , G11C11/404 , G11C11/406 , G11C11/4097
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

7. 发明申请

US20050013163A1 Semiconductor memory cell, array, architecture and device, and method of operating same 失效
标题翻译：半导体存储器单元，阵列，架构和器件及其操作方法
公开(公告)号：US20050013163A1
公开(公告)日：2005-01-20
申请号：US10829877
申请日：2004-04-22
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/404 , G11C16/04 , G11C16/28 , H01L20060101 , H01L27/108
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“1”）。可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

8. 发明授权

US07733693B2 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US07733693B2
公开(公告)日：2010-06-08
申请号：US12082020
申请日：2008-04-08
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关源线。

9. 发明授权

US07085156B2 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US07085156B2
公开(公告)日：2006-08-01
申请号：US11096970
申请日：2005-04-01
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

10. 发明申请

US20050157580A1 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20050157580A1
公开(公告)日：2005-07-21
申请号：US11079590
申请日：2005-03-14
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C20060101 , G11C8/00 , G11C11/00 , G11C11/404 , G11C11/406 , G11C11/4097
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

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