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1. 发明申请

US20110249499A1 Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same 有权
标题翻译：包括具有分段位线架构的存储器阵列的集成电路以及控制和/或操作的方法相同
公开(公告)号：US20110249499A1
公开(公告)日：2011-10-13
申请号：US13166291
申请日：2011-06-22
申请人： David Fisch , Michel Bron
发明人： David Fisch , Michel Bron
IPC分类号： G11C16/04
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.
摘要翻译：具有包括多个位线（例如，第一和第二位线）和多个位线段（例如，第一和第二位线）的存储单元阵列的集成电路器件（例如，逻辑器件或存储器件）段），其中每个位线段经由相关联的隔离电路被选择性地并且响应地耦合到或从其相关联的位线去耦。存储单元阵列还包括多个存储单元，其中每个存储单元包括具有第一区域，第二区域，体区域和经由相关联的字线段耦合到关联字线的栅极的晶体管。第一组存储器单元经由第一位线段耦合到第一位线，并且第二组存储器单元经由第二位线段耦合到第二位线。设置在每个位线段与其相关联位线之间的多个隔离电路响应地将相关联的位线段耦合到相关联的位线段或从相关联的位线断开相关联的位线段。

2. 发明授权

US07969779B2 Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same 有权
标题翻译：包括具有分段位线架构的存储器阵列和控制和/或操作相同方法的集成电路
公开(公告)号：US07969779B2
公开(公告)日：2011-06-28
申请号：US12467331
申请日：2009-05-18
申请人： David Fisch , Michel Bron
发明人： David Fisch , Michel Bron
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.
摘要翻译：具有包括多个位线（例如，第一和第二位线）和多个位线段（例如，第一和第二位线）的存储单元阵列的集成电路器件（例如，逻辑器件或存储器件）段），其中每个位线段经由相关联的隔离电路被选择性地并且响应地耦合到或从其相关联的位线去耦。存储单元阵列还包括多个存储单元，其中每个存储单元包括具有第一区域，第二区域，体区域和经由相关联的字线段耦合到关联字线的栅极的晶体管。第一组存储器单元经由第一位线段耦合到第一位线，并且第二组存储器单元经由第二位线段耦合到第二位线。设置在每个位线段与其相关联位线之间的多个隔离电路响应地将相关联的位线段耦合到相关联的位线段或从相关联的位线断开相关联的位线段。

3. 发明授权

US07542340B2 Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same 有权
标题翻译：包括具有分段位线架构的存储器阵列和控制和/或操作相同方法的集成电路
公开(公告)号：US07542340B2
公开(公告)日：2009-06-02
申请号：US11821848
申请日：2007-06-26
申请人： David Fisch , Michel Bron
发明人： David Fisch , Michel Bron
IPC分类号： G11C11/34
CPC分类号： H01L27/108 , G11C7/12 , G11C7/18 , G11C11/4097 , G11C2207/002 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is coupled to an associated bit line. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, responsively connect the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.
摘要翻译：具有包括多个位线（例如，第一和第二位线）和多个位线段（例如，第一和第二位线）的存储单元阵列的集成电路器件（例如，逻辑器件或存储器件）段），其中每个位线段耦合到相关联的位线。存储单元阵列还包括多个存储单元，其中每个存储单元包括具有第一区域，第二区域，体区域和经由相关联的字线段耦合到关联字线的栅极的晶体管。第一组存储器单元经由第一位线段耦合到第一位线，并且第二组存储器单元经由第二位线段耦合到第二位线。设置在每个位线段与其相关位线之间的多个隔离电路响应地将相关联的位线段连接到相关联的位线段或将其与相关联的位线断开。

4. 发明授权

US5557743A Protection circuit for a microprocessor 失效
标题翻译：微处理器保护电路
公开(公告)号：US5557743A
公开(公告)日：1996-09-17
申请号：US223484
申请日：1994-04-05
申请人： Raul Pombo , Jaime Borras , Michel Bron
发明人： Raul Pombo , Jaime Borras , Michel Bron
IPC分类号： G06F12/14 , G11C8/20 , G06F11/34
CPC分类号： G06F12/1433 , G11C8/20
摘要： Electronic devices using microprocessors requiring additional external memory can have security protection for the microprocessors while in an expanded mode of operation. A microprocessor having a security access circuit allows executable code to be stored in a peripheral storage device, such as external EPROM, while maintaining protection to the microprocessor EEPROM by monitoring if an instruction code is generated from an internal memory source or an external memory source.
摘要翻译：使用需要附加外部存储器的微处理器的电子设备可以在扩展的操作模式下对微处理器提供安全保护。具有安全访问电路的微处理器允许将可执行代码存储在诸如外部EPROM的外围存储设备中，同时通过监视从内部存储器源或外部存储器源产生指令代码来保护对微处理器EEPROM的保护。

5. 发明授权

US4841133A Data card circuits 失效
标题翻译：数据卡电路
公开(公告)号：US4841133A
公开(公告)日：1989-06-20
申请号：US175390
申请日：1988-03-30
申请人： Anil Gercekci , Michel Bron , Peter D. Hudson
发明人： Anil Gercekci , Michel Bron , Peter D. Hudson
IPC分类号： G06F21/77 , G06K19/073 , G07F7/10
CPC分类号： G07F7/1008 , G06F21/77 , G06K19/073 , G06K19/07363 , G06K19/07372 , G06Q20/3558 , G06F2221/2105
摘要： An integrated circuit for a data or "smart" card includes a non-volatile memory (8) having a transport code preprogrammed therein, control circuitry (10), a comparator (24) for comprising an externally-applied code and the transport code, and a fuse (26) which is blown if the two codes match thereby allowing the card to be initialised with a personal identification number and initial credit values. A second fuse (28) may also be provided which is blown if the two codes do not match and sensing means (32, 34) sense the status of the two fuses (26, 28) and block any further attempts to initialise the card if the second fuse (28) is blown and the first fuse (26) is not.

6. 发明申请

US20050174873A1 Semiconductor memory device and method of operating same 有权
公开(公告)号：US20050174873A1
公开(公告)日：2005-08-11
申请号：US11096970
申请日：2005-04-01
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C20060101 , G11C8/00 , G11C11/00 , G11C11/404 , G11C11/406 , G11C11/4097
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

7. 发明申请

US20050013163A1 Semiconductor memory cell, array, architecture and device, and method of operating same 失效
标题翻译：半导体存储器单元，阵列，架构和器件及其操作方法
公开(公告)号：US20050013163A1
公开(公告)日：2005-01-20
申请号：US10829877
申请日：2004-04-22
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/404 , G11C16/04 , G11C16/28 , H01L20060101 , H01L27/108
CPC分类号： G11C16/28 , G11C11/404 , G11C2211/4013 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“1”）。可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

8. 发明授权

US6128224A Method and apparatus for writing an erasable non-volatile memory 有权
标题翻译：用于写入可擦除非易失性存储器的方法和装置
公开(公告)号：US6128224A
公开(公告)日：2000-10-03
申请号：US289699
申请日：1999-04-09
申请人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
发明人： Bruce Lee Morton , Michel Bron , Alexis Marquot , Graham Stout , Eric Boulian
IPC分类号： G11C16/02 , G11C16/00 , G11C16/10 , G11C16/06
CPC分类号： G11C16/10
摘要： A method for writing data to non-volatile memory (50) involves alternately applying programming and erase voltages to a control gate wordline of a memory cell. A write includes programming and erasing bits (30, 31, . . . , 32, 33) in the memory array (56). After writing, a verify erase (VE) operation and a verify program (VP) operation are performed to determine if multiple cycles are necessary. The method also permits refreshing data in the array without transferring the data onto a data bus for improved security. In one embodiment, a three transistor EEPROM is written by providing a high voltage to the drain select of the selected wordline, while providing a low voltage to the drain select of other wordlines. Programming and erase voltages are applied to the control gate wordline of the selected wordline in cycles until the write is complete. The memory cell structure allows isolation of each bit in the array to avoid adverse effects on neighbor bits.
摘要翻译：一种将数据写入非易失性存储器（50）的方法包括交替地将编程和擦除电压施加到存储器单元的控制门字线。写入包括存储器阵列（56）中的编程和擦除位（30,31，...，32,33）。在写入之后，执行验证擦除（VE）操作和验证程序（VP）操作以确定是否需要多个周期。该方法还允许在阵列中刷新数据而不将数据传输到数据总线上以提高安全性。在一个实施例中，通过向所选字线的漏极选择提供高电压，同时向其它字线的漏极选择提供低电压来写入三晶体管EEPROM。编程和擦除电压以周期的形式施加到所选字线的控制栅极字线，直到写入完成。存储单元结构允许隔离阵列中的每个位，以避免对相邻位的不利影响。

9. 发明申请

US20070159911A1 Semiconductor memory device and method of operating same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20070159911A1
公开(公告)日：2007-07-12
申请号：US11713284
申请日：2007-03-02
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C8/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列的矩阵排列的多个半导体动态随机存取存储器单元。每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极身体区域。每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

10. 发明授权

US07187581B2 Semiconductor memory device and method of operating same 有权
公开(公告)号：US07187581B2
公开(公告)日：2007-03-06
申请号：US11079590
申请日：2005-03-14
申请人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
发明人： Richard Ferrant , Serguei Okhonin , Eric Carman , Michel Bron
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/404 , G11C7/18 , G11C8/08 , G11C11/406 , G11C11/40618 , G11C11/4097 , G11C2211/4016 , G11C2211/4065 , H01L21/84 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

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