专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080285549A1 SYNCHRONOUS READ CHANNEL 失效
标题翻译：同步读通道
公开(公告)号：US20080285549A1
公开(公告)日：2008-11-20
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

2. 发明授权

US5978162A Synchronous read channel integrated circuit employing a channel quality circuit for calibration 失效
标题翻译：采用通道质量电路进行校准的同步读通道集成电路
公开(公告)号：US5978162A
公开(公告)日：1999-11-02
申请号：US821174
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. A Channel Quality circuit accumulates various signals generated by the read channel, such as sample errors, gain errors, timing errors, etc., for use in calibrating the read channel components and estimating the bit error rate.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。通道质量电路积累由读通道产生的各种信号，例如采样误差，增益误差，定时误差等，用于校准读通道分量并估计误码率。

3. 发明授权

US5844738A Synchronous read channel employing a sequence detector with programmable detector levels 失效
标题翻译：采用具有可编程检测器电平的序列检测器的同步读通道
公开(公告)号：US5844738A
公开(公告)日：1998-12-01
申请号：US821175
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a trellis type sequence detector matched to the partial response. The trellis sequence detector comprises programmable detector levels which allows for maximum flexibility in matching the sequence detector to the partial response.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列从使用与部分响应匹配的格子型序列检测器的滤波样本值。网格序列检测器包括可编程检测器级别，其允许在将序列检测器与部分响应匹配时具有最大的灵活性。

4. 发明授权

US07885255B2 Synchronous read channel 有权
公开(公告)号：US07885255B2
公开(公告)日：2011-02-08
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

5. 发明授权

US07379452B2 Synchronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US07379452B2
公开(公告)日：2008-05-27
申请号：US10028871
申请日：2001-12-21
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特性，容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。公开了包括在单个集成电路中并入模拟量以及读取通道的数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂性的可编程修改维特比检测器的实施例。

6. 发明授权

US07957370B2 Synchronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US07957370B2
公开(公告)日：2011-06-07
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

7. 发明授权

US6021011A Synchronous read channel employing a digital center frequency setting for a variable frequency oscillator in discrete time timing recovery 失效
标题翻译：在离散时间定时恢复中采用可变频率振荡器的数字中心频率设置的同步读取通道
公开(公告)号：US6021011A
公开(公告)日：2000-02-01
申请号：US822603
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。读通道内的离散时间定时恢复包括用于产生采样时钟的可变频率振荡器（VFO）。 VFO的中心工作频率通过存储数字中心频率设置的可编程寄存器进行调整。从采样值计算相位误差，并与中心频率设置相结合，以控制VFO输出端采样时钟的频率和相位。

8. 发明授权

US5424881A Synchronous read channel 失效
公开(公告)号：US5424881A
公开(公告)日：1995-06-13
申请号：US12266
申请日：1993-02-01
申请人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
发明人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31 , G06F11/10 , G11B20/16
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

9. 发明授权

US5812334A Synchronous read channel employing discrete timing recovery, transition detector, and sequence detector 失效
标题翻译：采用离散定时恢复，转换检测器和序列检测器的同步读取通道
公开(公告)号：US5812334A
公开(公告)日：1998-09-22
申请号：US210302
申请日：1994-03-16
申请人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
发明人： Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

10. 发明授权

US5291499A Method and apparatus for reduced-complexity viterbi-type sequence detectors 失效
标题翻译：复杂度维特比型序列检测器的方法和装置
公开(公告)号：US5291499A
公开(公告)日：1994-03-01
申请号：US852015
申请日：1992-03-16
申请人： Richard T. Behrens , Kent D. Anderson , Neal Glover
发明人： Richard T. Behrens , Kent D. Anderson , Neal Glover
IPC分类号： G06F11/30 , G06F11/10 , G11B20/14 , G11B20/18 , H03H15/00 , H03H17/00 , H03H21/00 , H03M7/14 , H03M13/23 , H03M13/41 , H04B3/04 , H04L25/08 , H04L25/49 , H04L25/497 , H04L27/00 , G06F11/00
CPC分类号： G11B20/1426 , G11B20/1833 , H03M13/41 , H03M13/4107 , H04L25/4906 , H04L25/497
摘要： A Viterbi detector is modified to reduce its implementation complexity. A partial-response signal may be viewed as a sequence of expected samples generated from a finite-state-machine model. In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. In this invention, an ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator. The invention supports a wide range of sample models by making the expected sample sequence of an isolated medium transition programmable. The invention reduces the speed at which the detector circuitry must operate relative to the sample rate by allowing multiple samples to be processed simultaneously. Several reduced detectors for specific sample sequence models are presented for particular applications. The invention is applicable to other types of Viterbi detectors, such as decoders for convolutional codes.
摘要翻译：修改维特比检测器以减少其实现复杂度。部分响应信号可以被视为从有限状态机模型生成的预期样本的序列。在使用加法，比较，选择（ACS）方法实现的典型维特比解调器中，预期采样序列模型中的每个状态与硬件模块相关联，以执行向路径误差度量添加新的分支误差度量的功能，比较路径误差度量，并选择具有最低路径错误度量的路径。在本发明中，ACS模块可以具有与其动态相关联的两个或更多个序列模型状态，使得在某些时候一个序列模型状态与其相关联，并且在其他时间，另一个序列模型状态与其相关联。这减少了所需的ACS模块的数量，并且还降低了解调器的路径存储器的大小/复杂性，这些存储器必须存储每个ACS模块的一个路径。与原始的未导通的维特比解调器相比，可以选择一组序列模型状态来共享ACS模块而没有显着的性能损失。本发明通过使分离的介质跃迁的预期采样序列可编程化来支持范围广泛的样本模型。本发明通过允许同时处理多个采样来降低检测器电路相对于采样率运行的速度。针对特定应用提出了特定样品序列模型的几种降低检测器。本发明可应用于其它类型的维特比检测器，例如用于卷积码的解码器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式