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1. 发明授权

US5844738A Synchronous read channel employing a sequence detector with programmable detector levels 失效
标题翻译：采用具有可编程检测器电平的序列检测器的同步读通道
公开(公告)号：US5844738A
公开(公告)日：1998-12-01
申请号：US821175
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a trellis type sequence detector matched to the partial response. The trellis sequence detector comprises programmable detector levels which allows for maximum flexibility in matching the sequence detector to the partial response.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列从使用与部分响应匹配的格子型序列检测器的滤波样本值。网格序列检测器包括可编程检测器级别，其允许在将序列检测器与部分响应匹配时具有最大的灵活性。

2. 发明授权

US07885255B2 Synchronous read channel 有权
公开(公告)号：US07885255B2
公开(公告)日：2011-02-08
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

3. 发明授权

US07379452B2 Synchronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US07379452B2
公开(公告)日：2008-05-27
申请号：US10028871
申请日：2001-12-21
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating analog as well as digital functions of the read channel in a single integrated circuit, and embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特性，容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略来最大限度地提高数据恢复的可能性。公开了包括在单个集成电路中并入模拟量以及读取通道的数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂性的可编程修改维特比检测器的实施例。

4. 发明授权

US06313961B1 Method and apparatus for calibrating a synchronous read channel integrated circuit 失效
标题翻译：用于校准同步读通道集成电路的方法和装置
公开(公告)号：US06313961B1
公开(公告)日：2001-11-06
申请号：US08583295
申请日：1996-01-05
申请人： Alan J. Armstrong , Renee E. Wallerius , Richard T. Behrens , Charles J. Duey
发明人： Alan J. Armstrong , Renee E. Wallerius , Richard T. Behrens , Charles J. Duey
IPC分类号： G11B509
CPC分类号： G11B20/10481 , G11B5/00 , G11B5/09 , G11B20/10009 , G11B20/10055
摘要： A method and apparatus for calibrating the components of a Partial Response Read Channel (PRML) integrated circuit utilized in a magnetic storage device including a channel quality circuit, incorporated within the read channel IC, for automatically measuring the performance of each component as data is read by the channel. An error measurement for each component is generated as an indicator of the component's performance, such as a sample error generated by measuring the difference between the samples read by the channel and expected samples. The read channel components are programmed over a range of settings to determine the settings that generate the minimum error. By programming the components with settings corresponding to minimum error rates, the read channel is optimized. A programming device incorporated within the magnetic storage device and connected to the read channel IC executes a calibration program when the storage device is manufactured, repaired, and periodically to compensate for changes in the storage device and storage medium that occur over time.
摘要翻译：一种用于校准在包括读取通道IC中的通道质量电路的磁存储设备中使用的部分响应读通道（PRML）集成电路的组件的方法和装置，用于在读取数据时自动测量每个组件的性能通过频道。产生每个组件的误差测量，作为组件性能的指标，例如通过测量由通道读取的样品和预期样品之间的差异产生的样品误差。读通道组件通过一系列设置进行编程，以确定生成最小错误的设置。通过使用与最小错误率相对应的设置对组件进行编程，可以优化读取通道。结合在磁存储装置中并连接到读通道IC的编程装置在存储装置制造，修理和周期性地执行校准程序以补偿随时间发生的存储装置和存储介质的变化。

5. 发明授权

US5761212A Channel quality 失效
标题翻译：渠道质量
公开(公告)号：US5761212A
公开(公告)日：1998-06-02
申请号：US545965
申请日：1995-10-20
申请人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
发明人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , G11B20/18 , G11C29/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/18 , G11B20/1816 , G11B20/182 , G11B5/09
摘要： A measurement circuit is provided to obtain data for monitoring the quality of performance from a digital read channel. Elements of the digital read channel including a sequence detector are incorporated into an integrated circuit together with the measurement circuit. The measurement circuit relates digitized samples of readback data from a magnetic storage device to surrounding samples so that particular samples can be collected in accordance with their surroundings. The circuit includes a programmable time window which can be repeatedly opened for data collection. The circuit is designed to collect various types of data including the bit error rate, sample value, squared sample error, squared gain error, squared timing error, and the occurrences of sample error when it is outside an acceptable programmable threshold. The measurement circuit includes a signal generator for producing a test pattern that is first stored and then read to produce the digitized readback sample values. The measurement circuit also includes a conversion circuit for converting the test pattern to a sequence of expected sample values in accordance with a state machine model of the sequence detector. The sample value error results from a comparison of the readback sample value to the expected sample value.
摘要翻译：提供测量电路以获得用于从数字读取通道监视性能的数据。包括序列检测器的数字读通道的元件与测量电路一起并入集成电路中。测量电路将来自磁存储装置的回读数据的数字化样本与周围样品相关联，使得可以根据其周围环境收集特定样品。该电路包括可重复打开以供数据采集的可编程时间窗口。电路设计用于收集各种类型的数据，包括误码率，采样值，平方采样误差，平方增益误差，平方定时误差，以及采样误差超出可接受的可编程阈值时的出现。测量电路包括用于产生测试图案的信号发生器，其首先被存储然后被读取以产生数字化的回读采样值。测量电路还包括根据序列检测器的状态机模型将测试图案转换成预期样本值序列的转换电路。样本值误差来自于回读样本值与预期样本值的比较。

6. 发明授权

US08100318B1 Joining of tungsten alloys 有权
标题翻译：钨合金的连接
公开(公告)号：US08100318B1
公开(公告)日：2012-01-24
申请号：US12703815
申请日：2010-02-11
申请人： Animesh Bose , Morris F. Dilmore , Alan J. Armstrong
发明人： Animesh Bose , Morris F. Dilmore , Alan J. Armstrong
IPC分类号： B23K20/00
CPC分类号： B23K20/22 , B23K20/028
摘要： A process of making useful shapes by joining of tungsten alloys. Joining of tungsten heavy alloys which are alloys typically made from W—Ni—Fe is used. These alloys are typically manufactured by liquid phase sintering. This leads to difficulty in producing large length to diameter ratio parts that have some significant weight (such as penetrators). A “brick and mortar” approach is employed wherein smaller segments of this alloy (low length to diameter ratio) are joined to together to produce a larger part with higher length to diameter ratio.
摘要翻译：通过钨合金连接制作有用形状的工艺。使用通常由W-Ni-Fe制成的合金的钨重合金的连接。这些合金通常通过液相烧结制造。这导致难以生产具有一些显着重量的大直径比部件（例如穿透器）。采用“砖和砂浆”方法，其中该合金的较小部分（低长径比）被连接在一起以产生具有较高长径比的较大部分。

7. 发明授权

US6021011A Synchronous read channel employing a digital center frequency setting for a variable frequency oscillator in discrete time timing recovery 失效
标题翻译：在离散时间定时恢复中采用可变频率振荡器的数字中心频率设置的同步读取通道
公开(公告)号：US6021011A
公开(公告)日：2000-02-01
申请号：US822603
申请日：1997-03-19
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。读通道内的离散时间定时恢复包括用于产生采样时钟的可变频率振荡器（VFO）。 VFO的中心工作频率通过存储数字中心频率设置的可编程寄存器进行调整。从采样值计算相位误差，并与中心频率设置相结合，以控制VFO输出端采样时钟的频率和相位。

8. 发明授权

US6005731A Channel quality circuit employing a test pattern generator in a sampled amplitude read channel for calibration 失效
标题翻译：信道质量电路采用采样幅度读取通道中的测试码型发生器进行校准
公开(公告)号：US6005731A
公开(公告)日：1999-12-21
申请号：US844174
申请日：1997-04-18
申请人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
发明人： William R. Foland, Jr. , Richard T. Behrens , Alan J. Armstrong , Neal Glover
IPC分类号： G11B5/09 , G11B20/10 , G11B20/18
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/18 , G11B20/1816 , G11B20/182 , G11B5/09
摘要： A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
摘要翻译：一种信道质量电路，其被并入在磁存储系统中使用的采样幅度读取信道中，用于处理和累积来自各个读取信道分量的性能数据，其中，所述性能数据用于校准所述读取信道以在特定环境中操作，估计存储系统的误码率，并检测磁介质中的缺陷。信道质量电路产生写入存储系统的数字数据的测试模式。然后，当从存储系统读取测试图案时，信道质量电路从读取的信道分量累积性能数据。测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。门控逻辑被编程为仅累积感兴趣的特定性能数据。信道质量电路计算自动和互相关，平方误差和阈值比较。缺陷检测滤波器检测介质中的特定缺陷。为了预测存储系统的误码率，信道质量电路将噪声自相关数据，序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。

9. 发明授权

US5844920A Thermal asperity compensation using multiple sync marks for retroactive and split segment data synchronization in a magnetic disk storage system 失效
标题翻译：使用多个同步标记对磁盘存储系统中的追溯和分割段数据同步进行散热补偿补偿
公开(公告)号：US5844920A
公开(公告)日：1998-12-01
申请号：US745913
申请日：1996-11-07
申请人： Christopher P. Zook , Neal Glover , Alan J. Armstrong
发明人： Christopher P. Zook , Neal Glover , Alan J. Armstrong
IPC分类号： G11B5/012 , G11B20/14 , G11B20/18 , G11B27/30 , G11B20/10
CPC分类号： G11B20/1217 , G11B20/1426 , G11B20/1813 , G11B27/3027 , G11B5/012 , G11B2020/1476 , G11B2220/20
摘要： A magnetic disk storage system is disclosed wherein byte synchronization to sector data is achieved even when noise in the read channel, due for instance to a thermal asperity (TA), corrupts the primary preamble and/or sync mark fields or causes a loss of frequency or phase lock. The data sector format is modified to comprise at least one secondary sync mark in addition to the conventional primary sync mark recorded at the beginning of the data field. In this manner, when the primary sync mark becomes undetectable due to errors, or when byte synchronization is lost, the storage system can still synchronize to the data sector using the secondary sync mark. The secondary sync mark is preferably spaced apart from the primary sync mark with either a gap (no data) or user data inserted inbetween. In the latter embodiment, two methods are employed to recover user data inbetween the primary and secondary sync marks when the primary sync mark is undetectable: on-the-fly erasure pointer error correction, and buffering to facilitate retroactive synchronization. The secondary sync mark may optionally include a secondary preamble to facilitate phase locking to the data when the primary preamble is corrupted by errors. The present invention also provides "split segment" resynchronization for synchronizing a first section of data using a first mark, and retroactively synchronizing a second section of data using a following sync mark when synchronization is lost.
摘要翻译：公开了一种磁盘存储系统，其中即使由于例如热不平坦（TA）而导致的读通道中的噪声破坏了主前同步码和/或同步标记场，也导致频率损失，实现了与扇区数据的字节同步或锁相。修改数据扇区格式，除了在数据字段的开始处记录的常规主同步标记之外还包括至少一个辅助同步标记。以这种方式，当主同步标记由于错误而变得不可检测，或者当字节同步丢失时，存储系统仍然可以使用辅助同步标记与数据扇区同步。次同步标记优选地与主同步标记间隔开，间隙（无数据）或插入其间的用户数据。在后一实施例中，当主同步标记不可检测时，采用两种方法来恢复主同步标记和辅同步标记之间的用户数据：即时擦除指针错误校正和缓冲以便于追溯同步。辅助同步标记可以可选地包括辅助前同步码，以便在主要前同步码被错误破坏时便于锁定数据。本发明还提供了用于使用第一标记来同步第一部分数据的“分割段”重新同步，并且当同步丢失时使用后续同步标记追溯地同步第二数据段。

10. 发明授权

US07957370B2 Synchronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US07957370B2
公开(公告)日：2011-06-07
申请号：US12126188
申请日：2008-05-23
申请人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
发明人： Richard T. Behrens , Kent D. Anderson , Alan J. Armstrong , Trent Dudley , Bill R. Foland , Neal Glover , Larry D. King
IPC分类号： H04L12/50
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B2020/1476 , H03M13/31
摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
摘要翻译：公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道。集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

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