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1. 发明授权

US06978234B1 Configurable real prototype hardware using cores and memory macros 失效
标题翻译：可配置的真实原型硬件使用内核和内存宏
公开(公告)号：US06978234B1
公开(公告)日：2005-12-20
申请号：US09602369
申请日：2000-06-23
申请人： Robert P. Battaline , Emory D. Keller , Sebastian T. Ventrone
发明人： Robert P. Battaline , Emory D. Keller , Sebastian T. Ventrone
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22 , G06F11/26 , G06F13/00
CPC分类号： G06F11/261
摘要： A method of creating a prototype data processing system, by configuring a hardware development chip (HDC) according to user-defined settings, building user-defined logic adapted to function with the configured development chip, and allowing for the re-configuration of the HDC and user-defined logic after debugging. The HDC has several data processing macros including a processor core macro, a ROM emulation macro, a memory macro, and a bus macro. The macros may be configured by a configuration pin block which is connected to external configuration pins on the HDC. Customer logic is built using a field programmable gate array, which is interconnected with external ports of the HDC. The HDC and customer logic are verified using a debug port on the HDC, which is connected to a debug workstation. The invention allows a user to easily and quickly debug an application-specific integrated circuit (ASIC) design with a unique version of selected processor cores.
摘要翻译：一种创建原型数据处理系统的方法，通过根据用户定义的设置配置硬件开发芯片（HDC），构建适用于配置的开发芯片的用户定义逻辑，并允许重新配置HDC 和调试后的用户定义逻辑。 HDC具有多个数据处理宏，包括处理器核心宏，ROM仿真宏，存储器宏和总线宏。宏可以由连接到HDC上的外部配置引脚的配置引脚块来配置。客户逻辑使用与HDC的外部端口互连的现场可编程门阵列构建。 HDC和客户逻辑使用HDC上的调试端口进行验证，该调试端口连接到调试工作站。本发明允许用户使用所选择的处理器核心的唯一版本容易且快速地调试专用集成电路（ASIC）设计。

2. 发明授权

US06487701B1 System and method for AC performance tuning by thereshold voltage shifting in tubbed semiconductor technology 失效
标题翻译：通过液晶半导体技术中的阈值电压偏移进行交流性能调谐的系统和方法
公开(公告)号：US06487701B1
公开(公告)日：2002-11-26
申请号：US09711744
申请日：2000-11-13
申请人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
发明人： Alvar A. Dean , Jerry D. Hayes , Joseph A. Iadanza , Emory D. Keller , Sebastian T. Ventrone
IPC分类号： G06F1750
CPC分类号： G01R31/3163 , G01R31/2891
摘要： A system and method are described for separating the bulk connections for FETs on a semiconductor wafer from the supply rails, testing the wafer to determine if a shift in the threshold voltage, VT, of certain devices within the wafer, as defined by the bulk-wells, can remove an AC defect in the IC circuit, and tailoring the voltage or voltages applied to the bulk nodes, post-manufacture, such that the integrated circuit meets its performance targets or is sorted to a more valuable performance level. The method requires generating a gate level netlist of the IC's circuitry and performing timing calculations on these circuit netlists using static timing analyses, functional delay simulations, circuit activity analyses, and functional performance testing. The failures are then correlated to respective IC circuits, worst case slack circuits are investigated, and proposed changes to the threshold voltages are employed in the hardware.
摘要翻译：描述了一种系统和方法，用于将半导体晶片上的FET的体连接与电源轨分开，测试晶片以确定晶片内的某些器件的阈值电压VT是否偏移，孔可以去除IC电路中的AC缺陷，并且定制施加到散装节点的电压或电压，后制造，使得集成电路满足其性能目标或被分类到更有价值的性能水平。该方法需要生成IC电路的门级网表，并使用静态时序分析，功能延迟模拟，电路活动分析和功能性能测试来对这些电路网表执行定时计算。然后将故障与相应的IC电路相关联，最坏情况下调查松弛电路，并且在硬件中采用提出的阈值电压的改变。

3. 发明授权

US07752355B2 Asynchronous packet based dual port link list header and data credit management structure 有权
标题翻译：基于异步数据包的双端口链路列表头和数据信用管理结构
公开(公告)号：US07752355B2
公开(公告)日：2010-07-06
申请号：US10832658
申请日：2004-04-27
申请人： Emory D. Keller , Anthony J. Perri , Sebastian T. Ventrone
发明人： Emory D. Keller , Anthony J. Perri , Sebastian T. Ventrone
IPC分类号： G06F5/00
CPC分类号： G06F13/4059
摘要： An asynchronous data transfer interface is provided across a boundary that allows high bandwidth data transfers which are packet based as defined by PCI_Express architecture, and has general utility in processor-based applications like servers, desktop applications, and mobile applications. A shared set of multi-port RAM buffers allow both an application layer AL and a transaction layer TL access to a communication protocol layer in a defined process that allows both the application layer AL and the transaction layer TL to read and manage the buffers in a 16 byte boundary in a manner that allows a data credit to be decoupled from a header credit.
摘要翻译：跨越边界提供异步数据传输接口，允许高速带宽数据传输，这些数据传输是由PCI_Express架构定义的基于分组的，并且在基于处理器的应用程序（如服务器，桌面应用程序和移动应用程序）中具有通用功能。共享的一组多端口RAM缓冲器允许应用层AL和事务层TL在定义的过程中访问通信协议层，允许应用层AL和事务层TL两者读取和管理缓冲区中的缓冲区 16字节边界以允许从标题信用中分离数据信用的方式。

4. 发明申请

US20120168416A1 INTEGRATED CIRCUIT CHIP INCORPORATING EMBEDDED THERMAL RADIATORS FOR LOCALIZED, ON-DEMAND, HEATING AND A SYSTEM AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT CHIP 失效
标题翻译：集成电路芯片，用于本地化，点燃，加热和系统的嵌入式热分解器以及用于设计这种集成电路芯片的方法
公开(公告)号：US20120168416A1
公开(公告)日：2012-07-05
申请号：US12984638
申请日：2011-01-05
申请人： Richard S. Graf , Keishi Okamoto , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
发明人： Richard S. Graf , Keishi Okamoto , Faraydon Pakbaz , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： H05B3/00 , G06F17/50
CPC分类号： H05B1/0227 , G05D23/1934
摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.
摘要翻译：公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。温度传感器可以位于与TSZ相邻的半导体衬底中。热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。

5. 发明授权

US07937560B2 Processor pipeline architecture logic state retention systems and methods 有权
标题翻译：处理器管道架构逻辑状态保留系统和方法
公开(公告)号：US07937560B2
公开(公告)日：2011-05-03
申请号：US12121292
申请日：2008-05-15
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F15/76 , G06F1/00
CPC分类号： G06F9/3867 , G06F1/32 , G06F1/3287 , G06F11/1407 , G06F11/1441 , Y02D10/171
摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译：公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。比较器位于处理器流水线架构的两个阶段之间。存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。提供了与早期输出值相同的参考逻辑。逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态电容器。提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

6. 发明授权

US07895459B2 Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly 有权
标题翻译：一种用于预测间歇电力环境中的电力事件并且相应地调度集成电路的计算操作的系统和方法的结构
公开(公告)号：US07895459B2
公开(公告)日：2011-02-22
申请号：US11938899
申请日：2007-11-13
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.
摘要翻译：一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路。一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，根据历史日志预测后续功率事件，检索一个或者更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

7. 发明申请

US20110019819A1 SYSTEM AND METHOD OF MASKING ELECTROMAGNETIC INTERFERENCE (EMI) EMISSIONS OF A CIRCUIT 有权
标题翻译：屏蔽电路电磁干扰（EMI）排放的系统和方法
公开(公告)号：US20110019819A1
公开(公告)日：2011-01-27
申请号：US12507481
申请日：2009-07-22
申请人： Kerry Bernstein , Sebastian T. Ventrone
发明人： Kerry Bernstein , Sebastian T. Ventrone
IPC分类号： H04K1/02
CPC分类号： H04K3/825 , H04K3/42
摘要： A system is provided for securing information residing on a circuit (e.g., processor). In particular, a system and method is provided for masking electromagnetic interference (EMI) emissions emitting from a circuit using a random noise generator in combination with a low noise amplifier and antenna. The random number generator matches a frequency of a circuit to be protected, and generates a random signal to be superimposed on data. The low noise amplifier receives the random signal from the random number generator, and an antenna receives the random signal from the low noise amplifier and transmits the random signal to mask the data of the circuit to be protected.
摘要翻译：提供了用于保护驻留在电路（例如，处理器）上的信息的系统。特别地，提供了一种用于屏蔽使用随机噪声发生器与低噪声放大器和天线组合的从电路发射的电磁干扰（EMI）发射的系统和方法。随机数发生器匹配要保护的电路的频率，并产生要叠加在数据上的随机信号。低噪声放大器从随机数发生器接收随机信号，并且天线从低噪声放大器接收随机信号，并发送随机信号以掩蔽要被保护的电路的数据。

8. 发明授权

US07865862B2 Design structure for dynamically selecting compiled instructions 有权
标题翻译：动态选择编译指令的设计结构
公开(公告)号：US07865862B2
公开(公告)日：2011-01-04
申请号：US11937106
申请日：2007-11-08
申请人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
发明人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F9/3836 , G06F9/3885
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于动态选择编译指令进行执行的装置，该装置包括用于接收用于在第一执行单元上执行的静态指令的输入，以及在第二执行单元上接收用于执行的动态指令执行单位以及指令选择元件，其适于基于所述执行单元的当前状态来评估所述静态指令和动态指令的吞吐量性能，并分别在所述第一执行单元或所述第二执行单元上的运行时选择所述静态指令或用于执行的所述动态指令，基于指令的吞吐量性能。

9. 发明授权

US07791968B2 Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator 失效
标题翻译：基于部分耗尽的绝缘体上硅的状态确定数据保存装置中数据的历史状态
公开(公告)号：US07791968B2
公开(公告)日：2010-09-07
申请号：US11924955
申请日：2007-10-26
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/56 , G11C2029/0403 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1203
摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.
摘要翻译：公开了集成电路和设计结构。集成电路可以包括：数据保持装置; 电耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）装置; 以及耦合到所述PD SOI器件的测量装置，用于测量所述PD SOI器件的表示其体电压的状态，所述测量装置通信地耦合到计算装置，所述计算装置基于所述计算装置确定所述数据保持装置中的数据的历史状态测量PD SOI器件的状态。

10. 发明授权

US07755420B2 Intrinsic RC power distribution for noise filtering of analog supplies 失效
标题翻译：用于模拟电源噪声滤波的本征RC功率分配
公开(公告)号：US07755420B2
公开(公告)日：2010-07-13
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

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