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1. 发明授权

US08855969B2 Frequency guard band validation of processors 有权
标题翻译：处理器的频率保护带验证
公开(公告)号：US08855969B2
公开(公告)日：2014-10-07
申请号：US13170150
申请日：2011-06-27
申请人： Robert W. Berry, Jr. , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
发明人： Robert W. Berry, Jr. , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
IPC分类号： G01R31/28 , G06F11/24
CPC分类号： G01R31/2879 , G06F11/24
摘要： Whether validation of at least one of a plurality of previously validated processors on a first system produced data usable for computing a validation start frequency of an unvalidated processor on a second system is determined. If validation of at least one of the plurality of previously validated processors on the first system produced data usable for validating the unvalidated processor, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency.
摘要翻译：确定第一系统上的多个先前验证的处理器中的至少一个的验证是否产生可用于计算第二系统上未经验证的处理器的验证开始频率的数据。如果对第一系统上的多个先前验证的处理器中的至少一个的验证产生可用于验证未验证的处理器的数据，则可以至少部分地基于与系统参数数据相关联地计算与未验证的处理器相关联的验证开始频率具有在第一系统上验证的多个先前验证的处理器的子集。否则，至少部分地基于与未经验证的处理器相关联的测试仪参数数据来计算与未验证的处理器相关联的验证开始频率。无效处理器的保护频带频率的验证在验证开始频率处启动。

2. 发明申请

US20120330616A1 FREQUENCY GUARD BAND VALIDATION OF PROCESSORS 有权
标题翻译：加工商的频率防护带验证
公开(公告)号：US20120330616A1
公开(公告)日：2012-12-27
申请号：US13170150
申请日：2011-06-27
申请人： Robert W. Berry , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
发明人： Robert W. Berry , Diyanesh B. Chinnakkonda , Prasanna Jayaraman , Tony E. Sawan
IPC分类号： G06F11/30
CPC分类号： G01R31/2879 , G06F11/24
摘要： A frequency guard band validation unit can determine whether at least one of a plurality of previously validated processors was validated on a first system having a substantially similar configuration as a second system in which an unvalidated processor is being tested. If at least one of the plurality of previously validated processors was validated on the first system, a validation start frequency associated with the unvalidated processor can be computed based, at least in part, on system parametric data associated with a subset of the plurality of previously validated processors that were validated on the first system. Otherwise, the validation start frequency associated with the unvalidated processor is computed based, at least in part, on tester parametric data associated with the unvalidated processor. Validation of the guard band frequency for the unvalidated processor is initiated at the validation start frequency. This can reduce the overall validation cycle time.
摘要翻译：频率保护频带验证单元可以确定在具有基本相似配置的第一系统上验证多个先前验证的处理器中的至少一个是否是正在测试未验证的处理器的第二系统。如果多个先前验证的处理器中的至少一个在第一系统上被验证，则可以至少部分地基于与先前多个先前验证的处理器的子集相关联的系统参数数据来计算与未验证的处理器相关联的验证开始频率在第一个系统上验证的经过验证的处理器。否则，至少部分地基于与未经验证的处理器相关联的测试仪参数数据来计算与未验证的处理器相关联的验证开始频率。无效处理器的保护频带频率的验证在验证开始频率处启动。这可以减少总体验证周期时间。

3. 发明授权

US06324504B1 System and method for bit interleaving of full-rate speech data 有权
标题翻译：全速率语音数据的比特交织系统和方法
公开(公告)号：US06324504B1
公开(公告)日：2001-11-27
申请号：US09580654
申请日：2000-05-26
申请人： Sharif M. Sazzad , Jagannathan Bharath , Tony E. Sawan
发明人： Sharif M. Sazzad , Jagannathan Bharath , Tony E. Sawan
IPC分类号： G10L1902
CPC分类号： H04L1/0071
摘要： A memory-efficient system and method for generating data blocks “on demand” for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.
摘要翻译：用于TDMA数据脉冲串“按需”产生数据块的存储器有效系统和方法。在本发明的一个实施例中，GSM发射机模块将前向纠错（FEC）编码的全速率语音帧转换成TDMA数据块。发射机模块包括被配置为将FEC编码帧存储在当前帧缓冲器和先前帧缓冲器中的存储器，地址生成器被配置为在偶数时钟周期期间生成当前帧缓冲器中的字的地址，并且在前一帧中产生字的地址在奇数时钟周期内缓冲。为了产生字地址，地址发生器对位位置发生器提供的字偏移进行操作，位发生器也产生字内位偏移。存储器将地址生成器请求的数据字提供给多路复用器，该多路复用器从位位置发生器的字内位偏移中指示的每个数据字中选择一位。来自多路复用器的比特流形成数据块的比特重排序和帧交织数据。

4. 发明授权

US06195782B1 MLSE implementation using a general purpose DSP and shared hardware for a GSM application 失效
标题翻译：使用通用DSP和GSM应用程序的共享硬件实现MLSE
公开(公告)号：US06195782B1
公开(公告)日：2001-02-27
申请号：US09086098
申请日：1998-05-28
申请人： Muhammad M. Rahmatullah , Tony E. Sawan , Philip Yip
发明人： Muhammad M. Rahmatullah , Tony E. Sawan , Philip Yip
IPC分类号： H03M1303
CPC分类号： H03M13/6331 , H03M13/3961 , H03M13/41 , H03M13/6502 , H03M13/6569 , H04L1/0054
摘要： A digital signal processor (DSP), hardware module, and shared memory coupled together to perform Viterbi decoding on a sequence of received symbols. Given channel coefficients, the DSP calculates initial data for Viterbi processing: combination values for each possible state and branch product values for each possible symbol. These values are stored in shared memory for access by the hardware module. The DSP further calculates the first few stages of the Viterbi processing so path metrics are well defined for every state. Path metric values are also stored into the shared memory. The hardware module is optimized to perform calculations associated with a single stage of the Viterbi algorithm. The DSP invokes by the hardware module by passing a received sample to the hardware module. The hardware module calculates a survivor state value and minimizing path metric value for each state in the state space.
摘要翻译：耦合在一起的数字信号处理器（DSP），硬件模块和共享存储器，对接收的符号序列执行维特比解码。给定通道系数，DSP计算维特比处理的初始数据：每个可能状态的组合值和每个可能符号的分支乘积值。这些值存储在共享存储器中以供硬件模块访问。 DSP进一步计算维特比处理的前几个阶段，因此每个状态都很好地定义了路径度量。路径度量值也存储在共享存储器中。硬件模块被优化以执行与维特比算法的单级相关联的计算。通过将接收到的样本传递到硬件模块，DSP由硬件模块调用。硬件模块计算状态空间中的每个状态的幸存状态值并最小化路径度量值。

5. 发明授权

US6101465A System and method for bit interleaving of full-rate speech data 失效
标题翻译：全速率语音数据的比特交织系统和方法
公开(公告)号：US6101465A
公开(公告)日：2000-08-08
申请号：US873625
申请日：1997-06-12
申请人： Sharif M. Sazzad , Jagannathan Bharath , Tony E. Sawan
发明人： Sharif M. Sazzad , Jagannathan Bharath , Tony E. Sawan
IPC分类号： G10L19/00 , G10L19/02
CPC分类号： H04L1/0071
摘要： A memory-efficient system and method for generating data blocks "on demand" for TDMA data bursts. In one embodiment of the present invention, a GSM transmitter module converts forward error correction (FEC) coded full-rate speech frames into TDMA data blocks. The transmitter module includes a memory configured to store the FEC coded frames in a current frame buffer and a previous frame buffer, an address generator configured to generate addresses of words in the current frame buffer during even clock cycles and addresses of words in the previous frame buffer during odd clock cycles. To generate the word addresses, the address generator operates on word offsets provided by a bit position generator, which also generates intra-word bit offsets. The memory provides the data words requested by the address generator to a multiplexer, which the selects a bit from each of the data words as indicated by the intra-word bit offsets from the bit position generator. The stream of bits from the multiplexer forms the bit reordered and frame interleaved data for the data blocks.
摘要翻译：用于TDMA数据脉冲串“按需”产生数据块的存储器有效系统和方法。在本发明的一个实施例中，GSM发射机模块将前向纠错（FEC）编码的全速率语音帧转换成TDMA数据块。发射机模块包括被配置为将FEC编码帧存储在当前帧缓冲器和先前帧缓冲器中的存储器，地址生成器被配置为在偶数时钟周期期间生成当前帧缓冲器中的字的地址，并且在前一帧中产生字的地址在奇数时钟周期内缓冲。为了产生字地址，地址发生器对位位置发生器提供的字偏移进行操作，位发生器也产生字内位偏移。存储器将地址生成器请求的数据字提供给多路复用器，该多路复用器从位位置发生器的字内位偏移中指示的每个数据字中选择一位。来自多路复用器的比特流形成数据块的比特重排序和帧交织数据。

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