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1. 发明申请

US20130217199A1 METHOD FOR FABRICATING RESISTIVE MEMORY DEVICE 审中-公开
标题翻译：用于制造电阻式存储器件的方法
公开(公告)号：US20130217199A1
公开(公告)日：2013-08-22
申请号：US13580952
申请日：2012-04-16
申请人： Ru Huang , Shenghu Tan , Lijie Zhang , Yue Pan , Yinglong Huang , Gengyu Yang , Yu Tang , Jun Mao , Yimao Cai
发明人： Ru Huang , Shenghu Tan , Lijie Zhang , Yue Pan , Yinglong Huang , Gengyu Yang , Yu Tang , Jun Mao , Yimao Cai
IPC分类号： H01L21/02
CPC分类号： H01L45/04 , G11C13/0007 , G11C2013/0073 , G11C2213/15 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： The present invention discloses a method for fabricating a resistive memory, including: fabricating a bottom electrode over a substrate; partially oxidizing a metal of the bottom electrode through dry-oxygen oxidation or wet-oxygen oxidation to form a metal oxide with a thickness of 3 nm to 50 nm as a resistive material layer; finally fabricating a top electrode over the resistive material layer. The present invention omits a step of depositing a resistive material layer in a conventional method, so as to greatly reduce the process complexity. Meanwhile, a self alignment between the resistive material layer and the bottom electrode can be realized. A full isolation between devices may be ensured so as to obviate the parasite effects occurred in the conventional process methods. Meanwhile, the actual area and designed area of the device are ensured to be consistent.
摘要翻译：本发明公开了一种制造电阻式存储器的方法，包括：在衬底上制造底电极; 通过干氧氧化或湿氧氧化部分氧化底部电极的金属，形成厚度为3nm至50nm的金属氧化物作为电阻材料层; 最后在电阻材料层上制造顶部电极。本发明省略了以常规方法沉积电阻材料层的步骤，从而大大降低了工艺的复杂性。同时，可以实现电阻材料层和底部电极之间的自对准。可以确保器件之间的完全隔离，以便消除常规工艺方法中发生的寄生效应。同时，确保设备的实际面积和设计面积一致。

2. 发明授权

US08633465B2 Multilevel resistive memory having large storage capacity 有权
标题翻译：具有大存储容量的多电阻电阻存储器
公开(公告)号：US08633465B2
公开(公告)日：2014-01-21
申请号：US13513155
申请日：2012-02-08
申请人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
发明人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
IPC分类号： H01L47/00
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
摘要翻译：本发明公开了一种具有大存储容量的多电平电阻存储器，属于电阻式存储器的制造技术领域。电阻性存储器包括顶电极和底电极，以及插入在顶电极和底电极之间的多个开关层和有缺陷层的组合，其中，顶电极和底电极分别与开关层（诸如Ta 2 O 5，TiO 2，HfO 2的膜）和缺陷层（诸如Ti，Au，Ag的金属膜）介于切换层之间。通过使用本发明，可以提高电阻式存储器的存储容量。

3. 发明申请

US20130069031A1 MULTILEVEL RESISTIVE MEMORY HAVING LARGE STORAGE CAPACITY 有权
标题翻译：具有大容量存储容量的多电阻存储器
公开(公告)号：US20130069031A1
公开(公告)日：2013-03-21
申请号：US13513155
申请日：2012-02-08
申请人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
发明人： Ru Huang , Gengyu Yang , Yimao Cai , Yu Tang , Lijie Zhang , Yue Pan , Shenghu Tan , Yinglong Huang
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , G11C11/5685 , G11C13/0007 , H01L45/12 , H01L45/1233 , H01L45/146
摘要： The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.
摘要翻译：本发明公开了一种具有大存储容量的多电平电阻存储器，属于电阻式存储器的制造技术领域。电阻性存储器包括顶电极和底电极，以及插入在顶电极和底电极之间的多个开关层和有缺陷层的组合，其中，顶电极和底电极分别与开关层（诸如Ta 2 O 5，TiO 2，HfO 2的膜）和缺陷层（诸如Ti，Au，Ag的金属膜）介于切换层之间。通过使用本发明，可以提高电阻式存储器的存储容量。

4. 发明申请

US20140145139A1 TRANSPARENT FLEXIBLE RESISTIVE MEMORY AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：透明柔性电阻记忆及其制造方法
公开(公告)号：US20140145139A1
公开(公告)日：2014-05-29
申请号：US13581470
申请日：2012-02-22
申请人： Ru Huang , Yu Tang , Yimao Cai , Lijie Zhang , Gengyu Yang , Shenghu Tan , Yue Pan , Poren Tang
发明人： Ru Huang , Yu Tang , Yimao Cai , Lijie Zhang , Gengyu Yang , Shenghu Tan , Yue Pan , Poren Tang
IPC分类号： H01L45/00
CPC分类号： H01L45/149 , H01L45/1675 , H01L51/0591
摘要： The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained.
摘要翻译：本发明公开了一种透明柔性电阻式存储器及其制造方法。透明柔性电阻存储器包括透明柔性衬底，在衬底上具有MIM电容器结构的存储单元，其中存储单元的底电极和顶电极是透明和柔性的，中间电阻层是透明柔性膜的聚（对二甲苯）。聚（对二甲苯）具有优异的电阻特性。在该器件中，衬底，电极和中间电阻层均由透明柔性材料形成，从而获得可用于透明柔性电子系统中的完全透明的柔性电阻性存储器。

5. 发明授权

US08526242B2 Flash memory and fabrication method and operation method for the same 有权
标题翻译：闪存及其制作方法及操作方法相同
公开(公告)号：US08526242B2
公开(公告)日：2013-09-03
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

6. 发明申请

US20120113726A1 FLASH MEMORY AND FABRICATION METHOD AND OPERATION METHOD FOR THE SAME 有权
标题翻译：闪存及其制造方法和操作方法
公开(公告)号：US20120113726A1
公开(公告)日：2012-05-10
申请号：US13321120
申请日：2011-03-07
申请人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
发明人： Ru Huang , Yimao Cai , Shiqiang Qin , Qianqian Huang , Poren Tang , Yu Tang , Gengyu Yang
IPC分类号： G11C16/26 , H01L21/336 , H01L27/115
CPC分类号： H01L27/11556 , H01L29/7391 , H01L29/7889 , H01L29/8616
摘要： The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.
摘要翻译：本发明公开了一种闪存及其制作方法及其操作方法。闪速存储器包括两个垂直通道的存储单元，其中使用轻掺杂N型（或P型）硅作为衬底; 在硅表面的两端分别设置有P +区域（或N +区域），并且在两面之间设置与该表面垂直的2个沟道区域。在通道上设置由两个通道共享的N +区域（或P +区域）; 隧道氧化物层，多晶硅浮置栅极，块状氧化物层和多晶硅控制栅极，从内向外依次设置在每个沟道的外侧上; 并且多晶硅浮置栅极和多晶硅控制栅极通过侧壁氧化物层与P +区域隔离。整个器件是具有垂直通道的两位TFET型闪存，与现有的标准CMOS工艺具有更好的兼容性。与传统的基于MOSFET的闪存相比，根据本发明的闪速存储器具有诸如编程效率高，功耗低，穿透效果有效抑制和高密度等各种优点。

7. 发明申请

US20120199808A1 HIGH VOLTAGE-RESISTANT LATERAL DOUBLE-DIFFUSED TRANSISTOR BASED ON NANOWIRE DEVICE 有权
标题翻译：基于纳米器件的高耐压侧向双通道晶体管
公开(公告)号：US20120199808A1
公开(公告)日：2012-08-09
申请号：US13381633
申请日：2011-04-01
申请人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Al , Jiewen Fan
发明人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Al , Jiewen Fan
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0673 , B82Y10/00 , H01L29/0649 , H01L29/0692 , H01L29/16 , H01L29/66439 , H01L29/775
摘要： The present invention provides a high voltage-resistant lateral double-diffused transistor based on a nanowire device, which relates to the field of microelectronics semiconductor devices. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s). The invention can improve the high voltage-resistant capability of a lateral double-diffused transistor based on a silicon nanowire MOS transistor.
摘要翻译：本发明提供了一种基于纳米线器件的高耐压横向双扩散晶体管，其涉及微电子半导体器件的领域。横向双扩散MOS晶体管包括沟道区，栅极电介质，栅极区，源极区，漏极区，源极延伸区和漏极端S形漂移区，其中沟道区具有侧向圆柱形硅纳米线结构，其上均匀地覆盖一层栅极电介质，栅极区在栅极电介质上，栅极区和栅极电介质完全围绕沟道区，源极延伸区位于源区和漏极端S形漂移区域位于漏极区域和沟道区域之间，排水端S形漂移区域的平面图为单个或多个S形结构的形式，并且相对介电常数为1-4的绝缘材料填充在S形结构内。本发明可以提高基于硅纳米线MOS晶体管的横向双扩散晶体管的耐高压能力。

8. 发明授权

US08564031B2 High voltage-resistant lateral double-diffused transistor based on nanowire device 有权
标题翻译：基于纳米线器件的高耐压横向双扩散晶体管
公开(公告)号：US08564031B2
公开(公告)日：2013-10-22
申请号：US13381633
申请日：2011-04-01
申请人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Ai , Jiewen Fan
发明人： Ru Huang , Jibin Zou , Runsheng Wang , Gengyu Yang , Yujie Ai , Jiewen Fan
IPC分类号： H01L29/76
CPC分类号： H01L29/0673 , B82Y10/00 , H01L29/0649 , H01L29/0692 , H01L29/16 , H01L29/66439 , H01L29/775
摘要： The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).
摘要翻译：本发明提供了一种耐高压横向双扩散晶体管。横向双扩散MOS晶体管包括沟道区，栅极电介质，栅极区，源极区，漏极区，源极延伸区和漏极端S形漂移区，其中沟道区具有侧向圆柱形硅纳米线结构，其上均匀地覆盖一层栅极电介质，栅极区在栅极电介质上，栅极区和栅极电介质完全围绕沟道区，源极延伸区位于源区和漏极端S形漂移区域位于漏极区域和沟道区域之间，排水端S形漂移区域的平面图为单个或多个S形结构的形式，并且相对介电常数为1-4的绝缘材料填充在S形结构内。

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