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1. 发明申请

US20120259905A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 有权
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259905A1
公开(公告)日：2012-10-11
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
发明人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数移位由移位量产生单元生成的移位量而获得的量化尾数的移位单元和存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

2. 发明申请

US20120259903A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 审中-公开
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259903A1
公开(公告)日：2012-10-11
申请号：US13439932
申请日：2012-04-05
申请人： Ryuji KAN , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji KAN , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/49957
摘要： An arithmetic circuit for rounding pre-rounded data includes a first register to store first-format pre-rounded data that includes a mantissa of a fixed-precision floating-point number using a base-N numbering system, and includes an exponent for the mantissa, a second register to store rounding precision data indicative of precision for rounding the pre-rounded data, a leading zero counting unit to count consecutive zeros starting from a most significant bit of the mantissa stored in the first register, an exponent generating unit to generate a post-round exponent indicative of an exponent for a rounded significant by subtracting the number of zeros counted by the leading zero counting unit and the rounding precision data from a sum of one and the exponent stored in the first register, and an output register to store the post-round exponent and a rounding-add value that is to be added to a digit at which rounding is performed.
摘要翻译：用于舍入前置数据的算术电路包括：第一寄存器，用于存储使用基本N编号系统的包括固定精度浮点数的尾数的第一格式的前置数据，并且包括用于尾数的指数第二寄存器，用于存储指示用于舍入预舍数据的精度的舍入精度数据;前导零计数单元，用于从存储在第一寄存器中的尾数的最高有效位开始计数连续零;指数生成单元，用于生成指示通过从前导零计数单元计数的零的数目和来自存储在第一寄存器中的一个和的指数的舍入精度数据的舍入精度数据来指示舍入有效的指数的后向指数，以及输出寄存器存储后轮指数和要添加到执行舍入的数字的舍入加法值。

3. 发明申请

US20100095156A1 INFORMATION PROCESSING APPARATUS AND CONTROL METHOD 失效
标题翻译：信息处理装置和控制方法
公开(公告)号：US20100095156A1
公开(公告)日：2010-04-15
申请号：US12635896
申请日：2009-12-11
申请人： Ryuji KAN
发明人： Ryuji KAN
IPC分类号： G06F11/28
CPC分类号： G06F11/1064 , G06F9/30105 , G06F9/30127 , G06F9/30138 , G06F9/3865 , G06F11/2215 , G06F11/2236
摘要： A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output data; an instruction unit to issue a write instruction to write, to both register files, the output data and an error detection code for it, and first and second occurrence instructions; a first control unit to issue a first generation instruction when receiving the write instruction and the first occurrence instructions; and a first generation unit to generate a first simulated fault data to output it to the first register file when receiving the first generation instruction, and to output the output data and the error detection code to the first register file in absence of the first generation instruction. Similar second control and generation units are also provided mutatis mutandis.
摘要翻译：一种处理装置包括：第一和第二寄存器文件，后者保存前者中的一部分数据; 操作单元，用于对所述第二寄存器堆中的数据进行操作并输出数据; 发出写入指令的指令单元，向两个寄存器文件写入输出数据及其错误检测码，以及第一和第二次发生指令; 第一控制单元，当接收到写入指令和第一次发生指令时发出第一代指令; 以及第一生成单元，用于在接收到第一生成指令时生成第一模拟故障数据以将其输出到第一寄存器文件，并且在没有第一生成指令的情况下将输出数据和错误检测代码输出到第一寄存器堆。相应的第二控制和发电单位也经过必要的修改。

4. 发明申请

US20080229080A1 ARITHMETIC PROCESSING UNIT 审中-公开
标题翻译：算术处理单元
公开(公告)号：US20080229080A1
公开(公告)日：2008-09-18
申请号：US12037395
申请日：2008-02-26
申请人： Ryuji KAN , Tomohiro TANAKA , Toshio YOSHIDA
发明人： Ryuji KAN , Tomohiro TANAKA , Toshio YOSHIDA
IPC分类号： G06F9/302
CPC分类号： G06F9/30043 , G06F9/30076 , G06F9/30098 , G06F9/30101 , G06F9/3012 , G06F9/30127 , G06F9/3824 , G06F9/3826 , G06F9/384 , G06F9/3842 , G06F9/3867 , G06F9/462
摘要： An arithmetic processing unit includes a register file provided with multiple register windows, an arithmetic executor executes an instruction with data retained in the register file as an operand, and a current window pointer which retains address information specifying a register window which becomes a current window, and a controller. The controller controls the address information retained by the current window pointer is updated, when a window switching instruction for indicating switching of the current window has been decoded. The arithmetic executor reads data in a first register window specified by the address information before being updated and data in a second register window specified by the updated address information from the register file, after the decoding of said window switching instruction has been started until commit of the window switching instruction is started.
摘要翻译：算术处理单元包括具有多个寄存器窗口的寄存器文件，算术执行器执行具有作为操作数保留在寄存器堆中的数据的指令，以及保持指定成为当前窗口的寄存器窗口的地址信息的当前窗口指针，和控制器。当用于指示当前窗口的切换的窗口切换指令已被解码时，控制器控制由当前窗口指针保留的地址信息被更新。算术执行器在所述窗口切换指令的解码已经开始直到所述窗口切换指令的解码之后，在被更新之前由地址信息指定的第一寄存器窗口中的数据和由所述更新的地址信息由所述寄存器文件指定的第二寄存器窗口中的数据进行读取窗口切换指令开始。

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