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1. 发明授权

US07971029B2 Barrier synchronization method, device, and multi-core processor 有权
标题翻译：屏障同步方法，设备和多核处理器
公开(公告)号：US07971029B2
公开(公告)日：2011-06-28
申请号：US12638746
申请日：2009-12-15
申请人： Hideyuki Unno , Masaki Ukai , Matthew Depetro
发明人： Hideyuki Unno , Masaki Ukai , Matthew Depetro
IPC分类号： G06F15/177 , G06F15/76
CPC分类号： G06F9/52 , G06F9/522
摘要： A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
摘要翻译：用于实现多个处理器核心中属于同一同步组的至少2个处理器核心的屏障同步的屏障同步装置包括在具有多个处理器核心的多核处理器中，并且当该处理器核心中的两个或多个处理器核心多核处理器属于同一同步组，所包含的屏障同步装置用于实现屏障同步。

2. 发明授权

US08903881B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 有权
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08903881B2
公开(公告)日：2014-12-02
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42 , G06F7/483 , G06F7/499
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数偏移由移位量产生单元生成的移位量而获得的量化尾数的移位单元和用于存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

3. 发明授权

US08788561B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 失效
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08788561B2
公开(公告)日：2014-07-22
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

4. 发明授权

US08301969B2 Control method of information processing device and information processing device 失效
标题翻译：信息处理装置和信息处理装置的控制方法
公开(公告)号：US08301969B2
公开(公告)日：2012-10-30
申请号：US12198577
申请日：2008-08-26
申请人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
发明人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
IPC分类号： H03M13/00
CPC分类号： H04L1/0042 , G06F11/349 , H04L1/0047 , H04L25/4915
摘要： A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).
摘要翻译：发送侧设备（10）和接收侧设备（20）经由包括TAG位（31），数据位（32）和错误检测/校正ECC位（33）的总线（30）彼此连接。发送侧装置（10）使用冗余比特反相电路（14）反相对应于触发信号（41和42）的ECC比特（33）的不同比特。在接收侧设备（20）中，从错误检测/校正电路（22）接收到错误报告信号（26）的确定电路（24）从ECC位中的错误位的位置确定（33），所述触发信号（41和42）中的哪一个已经从所述发送侧装置（10）发送。

5. 发明申请

US20100095090A1 BARRIER SYNCHRONIZATION METHOD, DEVICE, AND MULTI-CORE PROCESSOR 有权
标题翻译： BARRIER同步方法，设备和多核处理器
公开(公告)号：US20100095090A1
公开(公告)日：2010-04-15
申请号：US12638746
申请日：2009-12-15
申请人： Hideyuki UNNO , Masaki Ukai , Matthew Depetro
发明人： Hideyuki UNNO , Masaki Ukai , Matthew Depetro
IPC分类号： G06F15/76 , G06F9/02 , G06F12/08
CPC分类号： G06F9/52 , G06F9/522
摘要： A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
摘要翻译：用于实现多个处理器核心中属于同一同步组的至少2个处理器核心的屏障同步的屏障同步装置包括在具有多个处理器核心的多核处理器中，并且当该处理器核心中的两个或多个处理器核心多核处理器属于同一同步组，所包含的屏障同步装置用于实现屏障同步。

6. 发明申请

US20080320376A1 ERROR DETECTION DEVICE 失效
标题翻译：错误检测装置
公开(公告)号：US20080320376A1
公开(公告)日：2008-12-25
申请号：US12200390
申请日：2008-08-28
申请人： Hideyuki UNNO
发明人： Hideyuki UNNO
IPC分类号： G06F11/00
CPC分类号： G06F11/073 , G06F11/0763 , G06F11/10 , G06F12/0802
摘要： A data buffer control unit obtains data from a cache according to a command retained in a command queue retaining a command(s) for reading data from the cache, and a magic ID generation circuit generates a magic ID. The data buffer control unit assigns the data obtained from the cache with the magic ID, writes the assigned data to a data buffer, and returns the magic ID to the command queue. When the data buffer control unit receives a read request and the magic ID which is returned to the command queue, it reads the data, which corresponds to the read request, from the command queue and compares the magic ID assigned in the read data and the received magic ID. If the two magic IDs compared by the data buffer control unit are not identical, a packet generator detects an error and reports the error to a host.
摘要翻译：数据缓冲器控制单元根据保存在用于从高速缓存读取数据的命令的命令队列中保留的命令从高速缓存获取数据，并且魔术ID生成电路生成魔术ID。数据缓冲器控制单元将从缓存获得的数据分配给魔术ID，将分配的数据写入数据缓冲器，并将魔术ID返回到命令队列。当数据缓冲器控制单元接收到读取请求和返回到命令队列的魔术ID时，它从命令队列中读取与读取请求对应的数据，并将读取的数据中分配的魔术ID和收到魔法ID。如果由数据缓冲器控制单元比较的两个魔术ID不相同，则分组生成器检测到错误并向主机报告错误。

7. 发明申请

US20080320201A1 CENTRAL PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：中央处理设备及其控制方法及信息处理系统
公开(公告)号：US20080320201A1
公开(公告)日：2008-12-25
申请号：US12199004
申请日：2008-08-27
申请人： Hideyuki UNNO , Masaki Ukai
发明人： Hideyuki UNNO , Masaki Ukai
IPC分类号： G06F13/28
CPC分类号： G06F12/0607 , G06F13/1647
摘要： A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.
摘要翻译：在系统控制器300的控制下，包括存储介质400和I / O设备500的多个系统控制器300通过多个系统总线200连接到CPU节点100.CPU节点100执行用于分配对系统总线200（即，系统控制器300）的存储器访问的存储器交错。在执行对I / O设备500的I / O访问时，CPU节点100首先向代表系统控制器300（SC0）询问哪个系统总线200（即，系统控制器300）具有目标I / O 然后对来自SC0的响应中返回的系统总线200执行实际的I / O访问。即使当CPU节点100在存储器映射的I / O的情况下执行存储器交错时，CPU节点100也不需要管理I / O设备500的位置信息。

8. 发明授权

US08910004B2 Information processing apparatus, and method of controlling information processing apparatus 有权
标题翻译：信息处理装置以及信息处理装置的控制方法
公开(公告)号：US08910004B2
公开(公告)日：2014-12-09
申请号：US13612098
申请日：2012-09-12
申请人： Hideyuki Unno
发明人： Hideyuki Unno
IPC分类号： H03M13/00 , G06F11/00 , G06F11/10
CPC分类号： G06F11/1016 , G06F11/004
摘要： A mark adding unit adds first information that is erroneously generated error detecting data of first data stored in a first storage area of a memory to the first data and adds second information that is erroneously generated error detecting information of second data stored in a second storage area to the second data. A mark removing unit removes the second information in the second data by rewriting the second information with the error detecting information of the second data without rewriting the first information in the first data when the second storage area out of the first storage area and the second storage area is configured to be usable. An error detecting unit performs an error detecting process of read-out data using information that is added to the read-out data in a case where the data stored in the memory is read out.
摘要翻译：标记添加单元将存储在存储器的第一存储区域中的第一数据的误差检测数据的第一信息添加到第一数据，并且将存储在第二存储区域中的错误地生成的第二数据的错误检测信息的第二信息到第二个数据。标记删除单元通过用第二数据的错误检测信息重写第二信息而不在第一存储区域和第二存储器中的第二存储区域中重新写入第一数据中的第一信息时，去除第二数据中的第二信息区域被配置为可用。在读出存储在存储器中的数据的情况下，错误检测单元使用附加到读出数据的信息来执行读出数据的错误检测处理。

9. 发明申请

US20120259906A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 失效
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259906A1
公开(公告)日：2012-10-11
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

10. 发明申请

US20120259905A1 ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT 有权
标题翻译：算术电路，算术处理装置和控制算术电路的方法
公开(公告)号：US20120259905A1
公开(公告)日：2012-10-11
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
发明人： Ryuji KAN , Hideyuki UNNO , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数移位由移位量产生单元生成的移位量而获得的量化尾数的移位单元和存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

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