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1. 发明授权

US09270507B2 Stacked comparator topology for multi-level signaling 有权
标题翻译：用于多级信令的堆叠比较器拓扑
公开(公告)号：US09270507B2
公开(公告)日：2016-02-23
申请号：US14162648
申请日：2014-01-23
申请人： Samsung Display Co., Ltd.
发明人： Mohammad Hekmat
IPC分类号： H04L25/34 , H04L27/06 , H03M5/20 , H04L25/49 , H04L25/06 , H04L25/03 , H03M1/00 , H03M1/36
CPC分类号： H04L27/06 , H03M1/002 , H03M1/361 , H03M5/20 , H04L25/03878 , H04L25/066 , H04L25/4917
摘要： A system and method for detecting signal levels in a multi-level signaling receiver. In one embodiment, a plurality of comparators, each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states current flows through FETs of the plurality of differential pairs in series, resulting in a reduction in power consumption.
摘要翻译：一种用于检测多级信令接收机中的信号电平的系统和方法。在一个实施例中，每个包括差分对（例如差分对的场效应晶体管（FET））的多个比较器以堆叠配置组装，使得在一些状态下，电流流过多个差分对的FET 系列，导致功耗降低。

2. 发明申请

US20150116299A1 BODY-BIASED SLICER DESIGN FOR PREDICTIVE DECISION FEEDBACK EQUALIZERS 有权
标题翻译： BODY-BIASED SLICER设计用于预测决策反馈均衡器
公开(公告)号：US20150116299A1
公开(公告)日：2015-04-30
申请号：US14340463
申请日：2014-07-24
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Mohammad Hekmat , Amir Amirkhany
IPC分类号： H04L25/03 , H03M1/70 , G09G5/00 , H03M1/00
CPC分类号： H04L25/03057 , G09G5/006 , G09G2310/0297 , G09G2330/021 , H03M1/002 , H03M1/70 , H04L25/03146 , H04L25/03878
摘要： A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.
摘要翻译：使用一个或多个场效应晶体管（FET）的体偏置来提供预测抽头的偏移的预测判决反馈均衡器。在一个实施例中，预测判决反馈均衡器的预测抽头包括由差分放大器配置中的两个FET组成的差分放大器，并且控制一个或两个FET的体偏置以在差分放大器中提供偏移。在一个实施例中，驱动DAC电阻器的电流DAC用于提供体偏置电压，并且包括形成最大可能DAC输出电压的复制电路的反馈电路用于控制电流DAC的电流源的偏置。

3. 发明申请

US20140314171A1 MISMATCHED DIFFERENTIAL CIRCUIT 有权
标题翻译：不匹配的差分电路
公开(公告)号：US20140314171A1
公开(公告)日：2014-10-23
申请号：US14061637
申请日：2013-10-23
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Mohammad Hekmat , Amir Amirkhany
IPC分类号： H03F3/45 , H04L25/49
CPC分类号： H03F3/45179 , H03F3/45183 , H03K5/082 , H04L25/4917
摘要： A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.
摘要翻译：一种差分放大器，包括：包括第一晶体管的第一放大器支路和包括第二晶体管的第二放大器支路。这里，第一晶体管被配置为具有与第二晶体管的体电势不同的体电位。第一放大器支路和第二放大器支路在一起可以被配置为差分放大接收到的差分输入信号。差分放大器可以被配置为具有对应于第一晶体管的体电势与第二晶体管的体电势之间的差的输入偏移电压。差分放大器可以处于比较器的输入级。

4. 发明申请

US20190265278A1 LOW OVERHEAD ON CHIP SCOPE 审中-公开
公开(公告)号：US20190265278A1
公开(公告)日：2019-08-29
申请号：US16054609
申请日：2018-08-03
申请人： Samsung Display Co., Ltd.
发明人： Da Wei , Mohammad Hekmat , Valentin Abramzon , Amir Amirkhany
IPC分类号： G01R13/02 , H03M3/00 , H03M1/06 , H03F3/387 , H03F3/45 , H03M1/12
摘要： An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.

5. 发明授权

US10476707B2 Hybrid half/quarter-rate DFE 有权
公开(公告)号：US10476707B2
公开(公告)日：2019-11-12
申请号：US16058896
申请日：2018-08-08
申请人： Samsung Display Co., Ltd.
发明人： Anup P. Jose , Amir Amirkhany , Mohammad Hekmat
IPC分类号： H03H7/30 , H04L25/03 , H03K3/356
摘要： A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

6. 发明申请

US20190272804A1 METHOD AND APPARATUS FOR DUTY-CYCLE CORRECTION OF HIGH SPEED I/O 审中-公开
公开(公告)号：US20190272804A1
公开(公告)日：2019-09-05
申请号：US16057037
申请日：2018-08-07
申请人： Samsung Display Co., Ltd.
发明人： Amir Amirkhany , Mohammad Hekmat
IPC分类号： G09G5/00 , H03K21/38 , H03K3/017
摘要： A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

7. 发明授权

US10401391B1 Low overhead on chip scope 有权
公开(公告)号：US10401391B1
公开(公告)日：2019-09-03
申请号：US16054609
申请日：2018-08-03
申请人： Samsung Display Co., Ltd.
发明人： Da Wei , Mohammad Hekmat , Valentin Abramzon , Amir Amirkhany
IPC分类号： H03M3/00 , H03M1/12 , H03F3/387 , H03F3/45 , H03M1/06 , G01R13/02
摘要： An on-chip scope and a method for operating the on-chip scope. The on-chip scope includes a provision for operating in one of two states, the effects of voltage offsets being different in the two states. A first voltage is measured in the first state, a second voltage is measured in the second state, and the two measurements are combined to generate a voltage estimate in which the effects of voltage offsets are reduced.

8. 发明授权

US09674008B2 Body-biased slicer design for predictive decision feedback equalizers 有权
公开(公告)号：US09674008B2
公开(公告)日：2017-06-06
申请号：US14340463
申请日：2014-07-24
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Mohammad Hekmat , Amir Amirkhany
IPC分类号： H04L25/03 , H03M1/70 , H03M1/00 , G09G5/00
CPC分类号： H04L25/03057 , G09G5/006 , G09G2310/0297 , G09G2330/021 , H03M1/002 , H03M1/70 , H04L25/03146 , H04L25/03878
摘要： A predictive decision feedback equalizer using body bias of one or more field effect transistors (FETs) to provide an offset for a predictive tap. In one embodiment, a predictive tap of the predictive decision feedback equalizer includes a differential amplifier composed of two FETs in a differential amplifier configuration, and the body bias of one or both FETs is controlled to provide an offset in the differential amplifier. In one embodiment a current DAC driving a DAC resistor is used to provide the body bias voltage, and a feedback circuit, including a replica circuit forming the maximum possible DAC output voltage, is used to control the bias of the current sources of the current DAC.

9. 发明授权

US09344305B2 PVT tolerant differential circuit 有权
标题翻译： PVT容差差分电路
公开(公告)号：US09344305B2
公开(公告)日：2016-05-17
申请号：US14254813
申请日：2014-04-16
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Mohammad Hekmat , Amir Amirkhany
IPC分类号： H04L25/49 , H04L25/06 , H03F3/45
CPC分类号： H04L25/4919 , H03F3/45183 , H03F2203/45032 , H03F2203/45244 , H04L25/06
摘要： An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.
摘要翻译：一种自动校准的差分放大器，包括：输入级差分放大器，被配置为接收输入差分信号，差分放大输入差分信号以产生输入级输出差分信号，并具有输入级偏置电流; 以及复制级差分放大器，被配置为响应于过程或环境变化自动校准输入级偏置电流。差分放大器可以包括在例如比较器和多电平接收器中。

10. 发明申请

US20140314173A1 PVT TOLERANT DIFFERENTIAL CIRCUIT 有权
标题翻译： PVT耐受差分电路
公开(公告)号：US20140314173A1
公开(公告)日：2014-10-23
申请号：US14254813
申请日：2014-04-16
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Mohammad Hekmat , Amir Amirkhany
IPC分类号： H04L25/49 , H04L25/06 , H03F3/45
CPC分类号： H04L25/4919 , H03F3/45183 , H03F2203/45032 , H03F2203/45244 , H04L25/06
摘要： An automatically calibrated differential amplifier including: an input stage differential amplifier configured to receive a input differential signal, to differentially amplify the input differential signal to generate an input stage output differential signal, and to have an input stage bias current; and a replica stage differential amplifier configured to automatically calibrate the input stage bias current in response to process or environmental variations. The differential amplifier may be included, for example, in a comparator and a multilevel receiver.
摘要翻译：一种自动校准的差分放大器，包括：输入级差分放大器，被配置为接收输入差分信号，差分放大输入差分信号以产生输入级输出差分信号，并具有输入级偏置电流; 以及复制级差分放大器，被配置为响应于过程或环境变化自动校准输入级偏置电流。差分放大器可以包括在例如比较器和多电平接收器中。

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