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1. 发明申请

US20160307767A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160307767A1
公开(公告)日：2016-10-20
申请号：US15099067
申请日：2016-04-14
申请人： Samsung Electronics Co., Ltd.
发明人： Dong-Hun Lee , Sunhom Steve Paak
IPC分类号： H01L21/308 , H01L21/306 , H01L21/762 , H01L29/66
CPC分类号： H01L21/3085 , H01L21/30604 , H01L21/3086 , H01L21/76224 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/1104 , H01L29/66545 , H01L29/66553 , H01L29/66795
摘要： A method of forming a semiconductor device includes sequentially forming a hard mask layer and a first sacrificial layer on a substrate, forming a first mandrel on the first sacrificial layer, forming a first spacer on both sidewalls of the first mandrel, removing the first mandrel, forming a second mandrel by etching the first sacrificial layer using the first spacer as an etch mask, forming a second spacer on both sidewalls of the second mandrel, removing the second mandrel, forming a hard mask pattern by patterning the hard mask layer using the second spacer as an etch mask, the hard mask pattern including first to ninth fin-type mask patterns extending to be parallel with each other in a first direction and sequentially spaced apart from each other in a second direction perpendicular to the first direction, removing the third, fifth and seventh fin-type mask patterns, forming first to sixth active patterns by etching the substrate using the hard mask pattern as an etch mask, and forming a first gate electrode extending in the second direction to intersect the first to fourth active patterns and a second gate electrode extending in the second direction to intersect the third to sixth active patterns and spaced apart from the first gate electrode in the first direction without intersecting the first and second active patterns.
摘要翻译：形成半导体器件的方法包括在衬底上依次形成硬掩模层和第一牺牲层，在第一牺牲层上形成第一芯棒，在第一芯棒的两个侧壁上形成第一间隔物，去除第一芯棒，通过使用第一间隔物作为蚀刻掩模蚀刻第一牺牲层来形成第二心轴，在第二心轴的两个侧壁上形成第二间隔物，去除第二心轴，通过使用第二心轴图案化硬掩模层形成硬掩模图案间隔物作为蚀刻掩模，所述硬掩模图案包括延伸为在第一方向上彼此平行并且在垂直于所述第一方向的第二方向上彼此间隔开的第一至第九鳍式掩模图案，第五和第七鳍型掩模图案，通过使用硬掩模图案作为蚀刻掩模蚀刻衬底来形成第一至第六有源图案，以及fo 将在第二方向上延伸以与第一至第四有源图案相交的第一栅极电极和第二栅电极沿第二方向延伸以与第三至第六有源图案相交并且在第一方向上与第一栅电极间隔开而不相交第一和第二活动模式。

2. 发明授权

US10403754B2 Semiconductor devices and methods of manufacturing the same 有权
公开(公告)号：US10403754B2
公开(公告)日：2019-09-03
申请号：US15970450
申请日：2018-05-03
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Dae Suk , Sunhom Steve Paak , Yeon-Ho Park , Dong-Ho Cha
IPC分类号： H01L29/78 , H01L29/786 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/66
摘要： Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.

3. 发明申请

US20160047853A1 TEST SYSTEM THAT PERFORMS SIMULTANEOUS TESTS OF MULTIPLE TEST UNITS 有权
标题翻译：同时测试多个测试单元的测试系统
公开(公告)号：US20160047853A1
公开(公告)日：2016-02-18
申请号：US14673490
申请日：2015-03-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： IN-WOOK OH , Chin Kim , Sunhom Steve Paak , Jae-Seok Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2607 , G01R31/2601 , G01R31/31722 , G01R31/318511 , G01R31/31926
摘要： A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.
摘要翻译：测试系统包括行解码器，列解码器，行测试控制器和测试电路。行解码器基于多个行输入信号来激活第一至第M行信号中的一个。列解码器基于多个列输入信号来激活第一至第N列信号中的一个。当行测试使能信号被激活时，行测试控制器首先输出第N列输出信号，这些信号被激活。当行测试使能信号被去激活时，行测试控制器分别输出第一至第N列信号作为第一至第N列输出信号。测试电路包括第一至第M行测试块，每个测试块包括第一至第N个测试单元。当行测试使能信号被激活时，测试电路同时执行包括在行测试块中的第一至第N测试单元的短测试。

4. 发明申请

US20180254341A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180254341A1
公开(公告)日：2018-09-06
申请号：US15970450
申请日：2018-05-03
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Dae Suk , Sunhom Steve Paak , Yeon-Ho Park , Dong-Ho Cha
IPC分类号： H01L29/78 , H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/417
CPC分类号： H01L29/785 , H01L29/0673 , H01L29/41733 , H01L29/41775 , H01L29/4236 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7856 , H01L29/78603 , H01L29/78696 , H01L2029/7858
摘要： Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.

5. 发明授权

US09575112B2 Test system that performs simultaneous tests of multiple test units 有权
标题翻译：同时测试多个测试单元的测试系统
公开(公告)号：US09575112B2
公开(公告)日：2017-02-21
申请号：US14673490
申请日：2015-03-30
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： In-Wook Oh , Chin Kim , Sunhom Steve Paak , Jae-Seok Yang
IPC分类号： G01R31/36 , G01R31/26 , G01R31/3185 , G01R31/317 , G01R31/319
CPC分类号： G01R31/2607 , G01R31/2601 , G01R31/31722 , G01R31/318511 , G01R31/31926
摘要： A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through M-th row signals based on plurality of row input signals. The column decoder activates one of first through N-th column signals based on plurality of column input signals. The row test controller outputs first through N-th column output signals, which are activated, when row test enable signal is activated. The row test controller outputs the first through N-th column signals as the first through N-th column output signals respectively when the row test enable signal is deactivated. The test circuit includes first through M-th row test blocks, each of which includes first through N-th test units. The test circuit simultaneously performs short test of the first through N-th test units included in row test block when the row test enable signal is activated.
摘要翻译：测试系统包括行解码器，列解码器，行测试控制器和测试电路。行解码器基于多个行输入信号来激活第一至第M行信号中的一个。列解码器基于多个列输入信号来激活第一至第N列信号中的一个。当行测试使能信号被激活时，行测试控制器首先输出第N列输出信号，这些信号被激活。当行测试使能信号被去激活时，行测试控制器分别输出第一至第N列信号作为第一至第N列输出信号。测试电路包括第一至第M行测试块，每个测试块包括第一至第N个测试单元。当行测试使能信号被激活时，测试电路同时执行包括在行测试块中的第一至第N测试单元的短测试。

6. 发明申请

US20170047243A1 SEMICONDUCTOR DEVICES HAVING ISOLATION INSULATING LAYERS AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有隔离绝缘层的半导体器件及其制造方法
公开(公告)号：US20170047243A1
公开(公告)日：2017-02-16
申请号：US15335743
申请日：2016-10-27
申请人： Samsung Electronics Co., Ltd.
发明人： HeonJong SHIN , Sungmin Kim , Byungseo Kim , Sunhom Steve Paak , Hyunjun Bae
IPC分类号： H01L21/762 , H01L21/265 , H01L21/324 , H01L29/66
CPC分类号： H01L21/76202 , H01L21/265 , H01L21/324 , H01L27/0886 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要： The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.
摘要翻译：本发明构思提供半导体器件及其制造方法。本发明构思的半导体器件可以包括散热片区域，其包括通过设置在其间的隔离绝缘层彼此分离和隔离的第一鳍片区域和第二鳍片区域，与第一鳍片区域交叉的第一栅极，与第二鳍片相交的第二栅极翅片子区域和与隔离绝缘层相交的第三栅极。

7. 发明授权

US09991387B2 Semiconductor devices 有权
公开(公告)号：US09991387B2
公开(公告)日：2018-06-05
申请号：US15172851
申请日：2016-06-03
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Dae Suk , Sunhom Steve Paak , Yeon-Ho Park , Dong-Ho Cha
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L29/417 , H01L29/786 , H01L29/06
CPC分类号： H01L29/785 , H01L29/0673 , H01L29/41733 , H01L29/41775 , H01L29/4236 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7856 , H01L29/78603 , H01L29/78696 , H01L2029/7858
摘要： Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.

8. 发明授权

US11201086B2 Semiconductor devices and methods of forming the same 有权
公开(公告)号：US11201086B2
公开(公告)日：2021-12-14
申请号：US16833885
申请日：2020-03-30
申请人： Samsung Electronics Co., Ltd.
发明人： Sung-Min Kim , Sunhom Steve Paak , Heon-Jong Shin , Dong-Ho Cha
IPC分类号： H01L29/78 , H01L21/8234
摘要： Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

9. 发明授权

US10204821B2 Semiconductor devices having isolation insulating layers and methods of manufacturing the same 有权
公开(公告)号：US10204821B2
公开(公告)日：2019-02-12
申请号：US15335743
申请日：2016-10-27
申请人： Samsung Electronics Co., Ltd.
发明人： HeonJong Shin , Sungmin Kim , Byungseo Kim , Sunhom Steve Paak , Hyunjun Bae
IPC分类号： H01L21/762 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/265 , H01L21/324
摘要： The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.

10. 发明授权

US10043873B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US10043873B2
公开(公告)日：2018-08-07
申请号：US15060174
申请日：2016-03-03
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Kyoung Hwan Yeo , Seonguk Park , Seungjae Lee , Doyoung Choi , Sunhom Steve Paak , Tae Eung Yoon , Dongho Cha , Ruiyi Chen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/40 , H01L29/66 , H01L27/11 , H01L29/417 , H01L29/78
摘要： Provided is a semiconductor device with a field effect transistor. The semiconductor device includes a substrate, an active pattern on the substrate, a gate electrode crossing the active pattern and a capping structure on the gate electrode. The capping structure includes first and second capping patterns that are sequentially stacked on the gate electrode. The second capping pattern completely covers a top surface of the first capping pattern, and a dielectric constant of the second capping pattern is greater than that of the first capping pattern.

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