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1. 发明授权

US09343156B1 Balancing programming speeds of memory cells in a 3D stacked memory 有权
标题翻译：平衡3D堆叠存储器中存储单元的编程速度
公开(公告)号：US09343156B1
公开(公告)日：2016-05-17
申请号：US14750250
申请日：2015-06-25
申请人： SanDisk Technologies Inc.
发明人： Man L Mui , Yongke Sun , Yingda Dong
IPC分类号： G11C11/34 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2211/5621
摘要： Programming techniques for a three-dimensional stacked memory device provide compensation for different intrinsic programming speeds of different groups of memory cells based on the groups' locations relative to the edge of a word line layer. A larger distance from the edge is associated with a faster programming speed. In one approach, the programming speeds are equalized by elevating a bit line voltage for the faster programming memory cells. Offset verify voltages which trigger a slow programming mode by elevating the bit line voltage can also be set based on the group locations. A programming speed can be measured during programming for a row or other group of cells to set the bit line voltage and/or the offset verify voltages. The compensation for the faster programming memory cells can also be based on their speed relative to the slower programming memory cells.
摘要翻译：用于三维堆叠存储器件的编程技术基于相对于字线层的边缘的组的位置来为不同组的存储器单元的不同固有编程速度提供补偿。距离边缘更大的距离与更快的编程速度相关联。在一种方法中，通过提高用于更快编程存储器单元的位线电压来使编程速度相等。也可以基于组位置来设置通过升高位线电压而触发缓慢编程模式的偏移验证电压。可以在针对一行或另一组单元的编程期间测量编程速度，以设置位线电压和/或偏移验证电压。更快编程存储单元的补偿也可以基于它们相对于较慢编程存储器单元的速度。

2. 发明授权

US09343171B1 Reduced erase-verify voltage for first-programmed word line in a memory device 有权
标题翻译：降低存储器件中第一个编程字线的擦除验证电压
公开(公告)号：US09343171B1
公开(公告)日：2016-05-17
申请号：US14617182
申请日：2015-02-09
申请人： SanDisk Technologies Inc.
发明人： Yongke Sun , Yingda Dong
IPC分类号： G11C11/34 , G11C16/34 , G11C16/04 , G11C16/14 , G11C16/26
CPC分类号： G11C16/3445 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C16/349
摘要： An erase operation for a memory cells in a block provides a consistent and sufficient erase depth regardless of the number of programmed word lines in the block. A lower erase-verify voltage is used for a first-programmed word line of a set of word lines than for remaining word lines in the set. As a result, the resistance of a memory cell of the first-programmed word line dominates during sensing of the NAND string so that the number of erase loops can be controlled in a predictable way regardless of the number of programmed word lines. The lower erase-verify voltage can be optimized so that it does not change the number of erase loops to complete an erase operation, compared to the case where a common erase-verify voltage is used on all word lines.
摘要翻译：块中的存储单元的擦除操作提供一致且足够的擦除深度，而与程序块中的编程字线数量无关。较低的擦除验证电压用于一组字线的第一编程字线比该组中的剩余字线。结果，在NAND串的感测期间，第一编程字线的存储单元的电阻占主导地位，使得可以以可预测的方式控制擦除循环的数量，而不管编程字线的数量如何。与在所有字线上使用公共擦除验证电压的情况相比，可以优化较低的擦除验证电压，使得其不改变擦除循环的数目以完成擦除操作。

3. 发明申请

US20160254047A1 PROGRAM VERIFY FOR NON-VOLATILE STORAGE 有权
标题翻译：程序验证非易失性存储
公开(公告)号：US20160254047A1
公开(公告)日：2016-09-01
申请号：US14632998
申请日：2015-02-26
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yongke Sun , Jiahui Yuan , Yingda Dong
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5642 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C16/32 , G11C16/34 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A non-volatile storage system includes a plurality of non-volatile storage elements arranged in two dimensional or three dimensional structures. The system applies programming to the non-volatile storage elements and performs verification of the programming. The verification includes performing a multi-strobe sensing operation to test for multiple data states while applying a common word line voltage.
摘要翻译：非易失性存储系统包括以二维或三维结构排列的多个非易失性存储元件。系统将编程应用于非易失性存储元件，并执行编程的验证。验证包括执行多次选通感测操作以在施加公共字线电压的同时测试多个数据状态。

4. 发明申请

US20140082437A1 Block And Page Level Bad Bit Line And Bits Screening Methods For Program Algorithm 有权
标题翻译：块和页级差位线和位筛选方法的程序算法
公开(公告)号：US20140082437A1
公开(公告)日：2014-03-20
申请号：US13622765
申请日：2012-09-19
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jun Wan , Bo Lei , Feng Pan , Yongke Sun
IPC分类号： G06F12/02 , G06F11/00
CPC分类号： G11C16/349 , G11C7/1006 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/10 , G11C16/24 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C29/025 , G11C29/44 , G11C2029/1204
摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.
摘要翻译：编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。可以存储识别有缺陷的NAND串的状态位。要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的位翻转回其原始值。在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

5. 发明授权

US09564213B2 Program verify for non-volatile storage 有权
标题翻译：程序验证非易失性存储
公开(公告)号：US09564213B2
公开(公告)日：2017-02-07
申请号：US14632998
申请日：2015-02-26
申请人： SANDISK TECHNOLOGIES INC.
发明人： Yongke Sun , Jiahui Yuan , Yingda Dong
IPC分类号： G11C16/00 , G11C11/56 , G11C16/34 , G11C16/04 , G11C16/32
CPC分类号： G11C11/5642 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C16/32 , G11C16/34 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A non-volatile storage system includes a plurality of non-volatile storage elements arranged in two dimensional or three dimensional structures. The system applies programming to the non-volatile storage elements and performs verification of the programming. The verification includes performing a multi-strobe sensing operation to test for multiple data states while applying a common word line voltage.
摘要翻译：非易失性存储系统包括以二维或三维结构排列的多个非易失性存储元件。系统将编程应用于非易失性存储元件，并执行编程的验证。验证包括执行多次选通感测操作以在施加公共字线电压的同时测试多个数据状态。

6. 发明授权

US08880964B2 Block and page level bad bit line and bits screening methods for program algorithm 有权
标题翻译：块和页级坏位线和位筛选方法的程序算法
公开(公告)号：US08880964B2
公开(公告)日：2014-11-04
申请号：US13622765
申请日：2012-09-19
申请人： SanDisk Technologies Inc.
发明人： Jun Wan , Bo Lei , Feng Pan , Yongke Sun
IPC分类号： G11C29/00 , G11C16/34
CPC分类号： G11C16/349 , G11C7/1006 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/10 , G11C16/24 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C29/025 , G11C29/44 , G11C2029/1204
摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.
摘要翻译：编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。可以存储识别有缺陷的NAND串的状态位。要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的比特翻转回其原始值。在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

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