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1. 发明授权

US09355713B2 Systems and methods for lower page writes 有权
标题翻译：较低页面写入的系统和方法
公开(公告)号：US09355713B2
公开(公告)日：2016-05-31
申请号：US14528892
申请日：2014-10-30
申请人： SanDisk Technologies Inc.
发明人： Jianmin Huang , Bo Lei , Jun Wan , Gerrit Jan Hemink , Steven T. Sprouse , Dana Lee
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C2211/5641
摘要： In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
摘要翻译：在多级单元（MLC）存储器阵列块中，首先写入低层页面，在任何高层页面之前，下层数据进行异或（XOR）操作，以便如果任何下层页面由ECC（UECC）无法校正），则可以使用XOR恢复页面。这些块中的下页可以以非顺序的顺序写入。

2. 发明申请

US20150117114A1 WORD LINE COUPLING FOR DEEP PROGRAM-VERIFY, ERASE-VERIFY AND READ 有权
标题翻译： WORD LINE COUPLING FOR DEEP PROGRAM-VERIFY，ERASE-VERIFY AND READ
公开(公告)号：US20150117114A1
公开(公告)日：2015-04-30
申请号：US14065092
申请日：2013-10-28
申请人： SanDisk Technologies Inc.
发明人： Jun Wan , Feng Pan , Bo Lei
IPC分类号： G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427 , G11C16/3445 , G11C16/3459
摘要： In a non-volatile storage system, a reduced voltage is provided on a selected word line during a sensing operation, using down coupling from one or more adjacent word lines. Voltages of one or more adjacent word lines of a selected word line are driven down while a voltage of the selected word line is floated. Capacitive coupling from the one or more adjacent word lines to the selected word line reduces the voltage of the selected word line. The capacitive coupling can be provided during a read, a program-verify test or an erase-verify test. The erase-verify test can be performed on cells of even-numbered word lines while capacitive coupling is provided by odd-numbered word lines, or on cells of odd-numbered word lines while capacitive coupling is provided by even-numbered word lines. Voltages of non-adjacent word lines can be provided at fixed, pass voltage levels.
摘要翻译：在非易失性存储系统中，使用来自一个或多个相邻字线的下联耦合，在感测操作期间在所选字线上提供降低的电压。所选字线的一个或多个相邻字线的电压在选定字线的电压浮动的同时被驱动。从所述一个或多个相邻字线到所选字线的电容耦合降低了所选字线的电压。可以在读取，程序验证测试或擦除验证测试期间提供电容耦合。在偶数字线提供电容耦合的情况下，可以对偶数字线的单元执行擦除验证测试，或者在偶数字线提供电容耦合的情况下，对奇数字线提供电容耦合，或在奇数字线的单元上进行擦除验证测试。可以以固定的通过电压电平提供非相邻字线的电压。

3. 发明授权

US08902652B1 Systems and methods for lower page writes 有权
标题翻译：较低页面写入的系统和方法
公开(公告)号：US08902652B1
公开(公告)日：2014-12-02
申请号：US14276925
申请日：2014-05-13
申请人： SanDisk Technologies Inc.
发明人： Jianmin Huang , Bo Lei , Jun Wan , Gerrit Jan Hemink , Steven T. Sprouse , Dana Lee
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C2211/5641
摘要： In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
摘要翻译：在多级单元（MLC）存储器阵列块中，首先写入低层页面，在任何高层页面之前，下层数据进行异或（XOR）操作，以便如果任何下层页面由ECC（UECC）无法校正），则可以使用XOR恢复页面。这些块中的下页可以以非顺序的顺序写入。

4. 发明申请

US20140063940A1 ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE 有权
标题翻译：在芯片动态读取级别扫描和错误检测非易失性存储
公开(公告)号：US20140063940A1
公开(公告)日：2014-03-06
申请号：US13761956
申请日：2013-02-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Wenzhou Chen , Zhenming Zhou , Jun Wan , Deepanshu Dutta , Yi-Chieh Chen , Dana Lee
IPC分类号： G11C16/10
CPC分类号： G06F11/1068 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/349 , G11C29/028 , G11C29/52
摘要： Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.
摘要翻译：公开了用于有效地编程非易失性存储器的技术。可以将第二页数据有效地编程到已经存储第一页的存储器单元中。数据可以从单个位单元有效地传送到多位单元。使用至少两个不同的读取级别读取存储器单元。将结果进行比较以确定计数在两次读取之间有多少个存储单元显示不同的结果。如果计数小于阈值，则来自存储器单元的数据被存储到一组数据锁存器中，而不尝试校正误读。如果计数不小于阈值，则来自存储器单元的数据被存储到数据锁存器集合中，试图校正误读。可以基于存储在该组数据锁存器中的数据来执行编程操作。

5. 发明授权

US09710325B2 On chip dynamic read level scan and error detection for nonvolatile storage 有权
公开(公告)号：US09710325B2
公开(公告)日：2017-07-18
申请号：US14681800
申请日：2015-04-08
申请人： SanDisk Technologies Inc.
发明人： Wenzhou Chen , Zhenming Zhou , Jun Wan , Deepanshu Dutta , Yi-Chieh Chen , Dana Lee
IPC分类号： G11C16/06 , G06F11/10 , G11C16/10 , G11C11/56 , G11C16/26 , G11C16/34 , G11C29/02 , G11C16/04 , G11C29/52
CPC分类号： G06F11/1068 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/349 , G11C29/028 , G11C29/52
摘要： Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

6. 再颁专利

USRE46264E1 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：USRE46264E1
公开(公告)日：2017-01-03
申请号：US14290905
申请日：2014-05-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06 , G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

7. 发明授权

US08937835B2 Non-volatile storage with read process that reduces disturb 有权
标题翻译：具有减少干扰的读取过程的非易失性存储
公开(公告)号：US08937835B2
公开(公告)日：2015-01-20
申请号：US13783781
申请日：2013-03-04
申请人： Sandisk Technologies Inc.
发明人： Bo Lei , Jun Wan , Feng Pan
IPC分类号： G11C11/34 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427
摘要： A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages.
摘要翻译：用于从非易失性存储器读取数据的装置和处理包括将读取的比较信号应用于NAND串的所选择的数据存储单元，将第一组一个或多个读取通过电压施加到所述NAND串的两端的未选择的数据存储单元 NAND串，并且将第二组一个或多个读取通过电压施加到NAND串的两端和所选数据存储单元的两侧之间的未选择的数据存储单元。第一组一个或多个读通道电压都高于一个或多个读通道电压的第一组。

8. 发明授权

US09047970B2 Word line coupling for deep program-verify, erase-verify and read 有权
标题翻译：用于深度程序验证，擦除验证和读取的字线耦合
公开(公告)号：US09047970B2
公开(公告)日：2015-06-02
申请号：US14065092
申请日：2013-10-28
申请人： SanDisk Technologies Inc.
发明人： Jun Wan , Feng Pan , Bo Lei
IPC分类号： G11C16/06 , G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427 , G11C16/3445 , G11C16/3459
摘要： In a non-volatile storage system, a reduced voltage is provided on a selected word line during a sensing operation, using down coupling from one or more adjacent word lines. Voltages of one or more adjacent word lines of a selected word line are driven down while a voltage of the selected word line is floated. Capacitive coupling from the one or more adjacent word lines to the selected word line reduces the voltage of the selected word line. The capacitive coupling can be provided during a read, a program-verify test or an erase-verify test. The erase-verify test can be performed on cells of even-numbered word lines while capacitive coupling is provided by odd-numbered word lines, or on cells of odd-numbered word lines while capacitive coupling is provided by even-numbered word lines. Voltages of non-adjacent word lines can be provided at fixed, pass voltage levels.
摘要翻译：在非易失性存储系统中，使用来自一个或多个相邻字线的下联耦合，在感测操作期间在所选字线上提供降低的电压。所选字线的一个或多个相邻字线的电压在选定字线的电压浮动的同时被驱动。从所述一个或多个相邻字线到所选字线的电容耦合降低了所选字线的电压。可以在读取，程序验证测试或擦除验证测试期间提供电容耦合。在偶数字线提供电容耦合的情况下，可以对偶数字线的单元执行擦除验证测试，或者在偶数字线提供电容耦合的情况下，对奇数字线提供电容耦合，或在奇数字线的单元上进行擦除验证测试。可以以固定的通过电压电平提供非相邻字线的电压。

9. 发明申请

US20140082437A1 Block And Page Level Bad Bit Line And Bits Screening Methods For Program Algorithm 有权
标题翻译：块和页级差位线和位筛选方法的程序算法
公开(公告)号：US20140082437A1
公开(公告)日：2014-03-20
申请号：US13622765
申请日：2012-09-19
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jun Wan , Bo Lei , Feng Pan , Yongke Sun
IPC分类号： G06F12/02 , G06F11/00
CPC分类号： G11C16/349 , G11C7/1006 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/00 , G11C16/10 , G11C16/24 , G11C16/3409 , G11C16/3413 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C16/3445 , G11C16/345 , G11C16/3459 , G11C29/025 , G11C29/44 , G11C2029/1204
摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.
摘要翻译：编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。可以存储识别有缺陷的NAND串的状态位。要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的位翻转回其原始值。在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

10. 发明授权

US09564233B1 Open block source bias adjustment for an incompletely programmed block of a nonvolatile storage device 有权
标题翻译：非易失性存储设备未完全编程块的开放源偏置调整
公开(公告)号：US09564233B1
公开(公告)日：2017-02-07
申请号：US15061919
申请日：2016-03-04
申请人： SanDisk Technologies, Inc.
发明人： Hoon Cho , Jun Wan , Yanjie Wang
IPC分类号： G11C11/34 , G11C16/16 , G11C16/26 , G11C16/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/3459 , G11C16/349 , G11C16/3495
摘要： Apparatuses, systems, methods, and computer program products are disclosed for adjusting a voltage level for a write operation on a partially programmed block of a nonvolatile storage device. A write module receives a request to perform a write operation for one or more storage cells of an partially programmed block of a nonvolatile storage device. A characteristic module determines whether a characteristic for a partially programmed block of a nonvolatile storage device satisfies a threshold. A voltage adjustment module adjusts a voltage level applied to one or more source lines connected to the one or more storage cells during a write operation in response to determining a characteristic satisfies a threshold.
摘要翻译：公开的装置，系统，方法和计算机程序产品用于调整非挥发性存储装置的部分编程块上的写入操作的电压电平。写入模块接收对非易失性存储设备的部分编程的块的一个或多个存储单元执行写入操作的请求。特征模块确定非易失性存储装置的部分编程块的特性是否满足阈值。响应于确定特性满足阈值，电压调节模块在写入操作期间调整施加到连接到一个或多个存储单元的一个或多个源极线的电压电平。

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