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1. 发明授权

US10304523B2 Semiconductor device comprising memory devices each comprising sense amplifier and memory cell 有权
公开(公告)号：US10304523B2
公开(公告)日：2019-05-28
申请号：US14705698
申请日：2015-05-06
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kiyoshi Kato , Tatsuya Onuki
IPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4097
摘要： A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

2. 发明授权

US10050060B2 Semiconductor device and electronic device 有权
公开(公告)号：US10050060B2
公开(公告)日：2018-08-14
申请号：US15591145
申请日：2017-05-10
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hidekazu Miyairi , Yuichi Sato , Yuji Asano , Tetsunori Maruyama , Tatsuya Onuki , Shuhei Nagatsuka
IPC分类号： H01L27/12 , H01L29/78 , H01L23/48 , H01L23/485 , H01L23/522 , H01L23/532 , H01L27/06 , H01L29/786 , H01L21/768 , H01L21/8258
摘要： To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

3. 发明授权

US10037798B2 Semiconductor device and method for driving semiconductor device 有权
公开(公告)号：US10037798B2
公开(公告)日：2018-07-31
申请号：US15603570
申请日：2017-05-24
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya Onuki
IPC分类号： G11C5/06 , G11C11/56 , G11C11/403 , G11C11/4091 , G11C11/4076
CPC分类号： G11C11/565 , G11C11/403 , G11C11/4076 , G11C11/4091
摘要： To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.

4. 发明授权

US09852787B2 Semiconductor device, electronic component, and electronic device 有权
公开(公告)号：US09852787B2
公开(公告)日：2017-12-26
申请号：US15464395
申请日：2017-03-21
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Takahiko Ishizu , Kiyoshi Kato , Tatsuya Onuki , Wataru Uesugi
IPC分类号： G11C11/419 , G11C5/14 , G06F3/06 , G11C14/00
CPC分类号： G11C5/147 , G06F3/0619 , G06F3/065 , G06F3/0685 , G11C11/419 , G11C14/0054
摘要： Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

5. 发明授权

US09715906B2 Bootstrap circuit and semiconductor device having bootstrap circuit 有权
公开(公告)号：US09715906B2
公开(公告)日：2017-07-25
申请号：US14502209
申请日：2014-09-30
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Takahiko Ishizu , Kiyoshi Kato , Yutaka Shionoiri , Tatsuya Onuki
IPC分类号： G11C5/14 , H01L21/8258 , H01L27/06 , H01L27/092 , H01L29/786 , H01L27/12 , H01L29/78
CPC分类号： G11C5/145 , H01L21/8258 , H01L27/0688 , H01L27/092 , H01L27/1225 , H01L29/785 , H01L29/7869 , H01L29/78696
摘要： A bootstrap circuit of which the capacitance of a bootstrap capacitor is small and which requires a shorter precharge period is provided. The bootstrap circuit includes transistors M41 and M42, capacitors BSC1 and BSC2, an inverter INV41, and keeper circuits 43 and 44. A signal OSG with a high voltage is generated from an input signal OSG_IN. As the signal OSG_IN is made a high level, a node SWG is made a high level by BSC1. After a signal BSE1 is made a high level and the node SWG is made a low level by the keeper circuit 44, a signal BSE2 is made a high level. By the capacitance coupling of BSC2, a voltage of an output terminal 22 increases.

6. 发明授权

US09673224B2 Semiconductor device 有权
公开(公告)号：US09673224B2
公开(公告)日：2017-06-06
申请号：US14515993
申请日：2014-10-16
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Shunpei Yamazaki , Shuhei Nagatsuka , Tatsuya Onuki , Yutaka Shionoiri , Kiyoshi Kato , Hidekazu Miyairi
IPC分类号： H01L27/12 , H01L29/423 , H01L29/786
CPC分类号： H01L27/1225 , H01L29/42384 , H01L29/7869 , H01L29/78696
摘要： To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, a barrier layer between the first transistor and the second transistor, a first electrode between the first transistor and the barrier layer, and a second electrode between the hairier layer and the second transistor and overlapping the first electrode with the barrier layer therebetween. A gate electrode of the first transistor, the first electrode, one of a source electrode and a drain electrode of the second transistor are electrically connected to one another. A channel is formed in a first semiconductor layer including a single crystal semiconductor in the first transistor. A channel is formed in a second semiconductor layer including an oxide semiconductor in the second transistor.

7. 发明授权

US09502094B2 Method for driving memory element 有权
标题翻译：驱动存储元件的方法
公开(公告)号：US09502094B2
公开(公告)日：2016-11-22
申请号：US13892479
申请日：2013-05-13
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya Onuki
IPC分类号： G11C11/40 , G11C14/00 , H01L27/11 , H01L27/12
CPC分类号： G11C11/40 , G11C14/0063 , H01L27/1108 , H01L27/1225
摘要： To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating stop of supply of power to the memory element for a short time. Data (potential) held in a node in a logic circuit can be swiftly saved on a node where one of a source and a drain of the transistor and one electrode of the capacitor included in a memory circuit are connected by lowering a potential of the other electrode of a capacitor before a transistor is turned on. By making a potential of the other electrode of the capacitor when the transistor is in an off state higher than a potential of the other electrode of the capacitor when the transistor is in an on state, a potential of the node can be reliably held even without supply of power.
摘要翻译：提供即使不提供电源也保持存储的逻辑状态的存储元件。通过在短时间内有助于停止对存储元件供电的功率来增加降低功耗的效果。保持在逻辑电路中的节点中的数据（电位）可以迅速地保存在晶体管的源极和漏极之一以及包含在存储器电路中的电容器的一个电极中的一个通过降低另一个的电位而连接的节点在晶体管导通之前的电容器的电极。当晶体管处于断开状态时，当晶体管处于导通状态时，通过使电容器的另一个电极的电位高于电容器的另一个电极的电位，即使没有供电。

8. 发明授权

US09467139B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09467139B2
公开(公告)日：2016-10-11
申请号：US14641708
申请日：2015-03-09
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya Onuki
IPC分类号： G11C7/00 , H03K17/687 , H03K17/16
CPC分类号： H03K17/687 , H01L27/0207 , H01L29/78693 , H03K17/161 , H03K2217/0036
摘要： A semiconductor device capable of reducing power consumption is provided. A writing potential is supplied to the cell 11 in which data rewriting is to be performed, whereby data is written. Meanwhile, in the cell 11 in which data rewriting is not to be performed, the data is transferred to the cell 12 and then the transferred data is rewritten to the cell 11. As a result, the data stored in the cell 11 in which data rewriting is not to be performed can be maintained without the reading and writing operation in a driver circuit. This results in a higher rewriting speed and lower power consumption in the driver circuit.
摘要翻译：提供能够降低功耗的半导体器件。将写入电势提供给要执行数据重写的单元11，从而写入数据。同时，在不执行数据重写的单元11中，将数据传送到单元12，然后将所传送的数据重写到单元11.结果，存储在单元11中的数据，其中数据在驱动电路中没有进行读写操作的情况下，不能进行重写。这导致驱动电路中更高的重写速度和更低的功耗。

9. 发明申请

US20140286073A1 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE 有权
标题翻译：用于驱动半导体器件的半导体器件和方法
公开(公告)号：US20140286073A1
公开(公告)日：2014-09-25
申请号：US14218058
申请日：2014-03-18
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Tatsuya Onuki
IPC分类号： G11C7/12
CPC分类号： G11C11/565 , G11C11/403 , G11C11/4076 , G11C11/4091
摘要： To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.
摘要翻译：提供一种可写入和读出所需电位的半导体器件。半导体器件包括第一晶体管（Tr），第二Tr和电容器。在半导体装置中，通过第一步骤和第二步骤执行写入数据的操作。在第一步骤中，将低电压施加到位线和第一布线以接通第一Tr和第二Tr。在第二步骤中，向第一布线施加第一电压，停止向位线施加低电压。通过第三步骤和第四步骤执行读取数据的操作。在第三步骤中，向第一布线施加高电压。在第四步骤中，停止向第一布线施加高电压，并且向电容器线施加低电压。

10. 发明申请

US20130314976A1 METHOD FOR DRIVING MEMORY ELEMENT 有权
标题翻译：驱动存储元件的方法
公开(公告)号：US20130314976A1
公开(公告)日：2013-11-28
申请号：US13892479
申请日：2013-05-13
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Tatsuya Onuki
IPC分类号： G11C11/40
CPC分类号： G11C11/40 , G11C14/0063 , H01L27/1108 , H01L27/1225
摘要： To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating stop of supply of power to the memory element for a short time. Data (potential) held in a node in a logic circuit can be swiftly saved on a node where one of a source and a drain of the transistor and one electrode of the capacitor included in a memory circuit are connected by lowering a potential of the other electrode of a capacitor before a transistor is turned on. By making a potential of the other electrode of the capacitor when the transistor is in an off state higher than a potential of the other electrode of the capacitor when the transistor is in an on state, a potential of the node can be reliably held even without supply of power.
摘要翻译：提供即使不提供电源也保持存储的逻辑状态的存储元件。通过在短时间内有助于停止对存储元件供电的功率来增加降低功耗的效果。保持在逻辑电路中的节点中的数据（电位）可以迅速地保存在晶体管的源极和漏极之一以及包含在存储器电路中的电容器的一个电极中的一个通过降低另一个的电位而连接的节点在晶体管导通之前的电容器的电极。当晶体管处于断开状态时，当晶体管处于导通状态时，通过使电容器的另一个电极的电位高于电容器的另一个电极的电位，即使没有供电。

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