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1. 发明授权

US09024668B1 Clock generator 有权
标题翻译：时钟发生器
公开(公告)号：US09024668B1
公开(公告)日：2015-05-05
申请号：US14189401
申请日：2014-02-25
申请人： SK Hynix Inc.
发明人： Seung Geun Baek , Hyun Woo Lee
IPC分类号： H03L7/06 , H03K5/06 , G05F1/46 , H03L7/08 , H03K3/012
CPC分类号： H03K5/06 , G05F1/46 , G11C7/222 , H03K5/003 , H03L7/0802 , H03L7/0805 , H03L7/0816
摘要： A clock generation circuit of a semiconductor apparatus includes a first clock generation unit configured to output a first signal which swings between a level of a power supply voltage and a level of a set voltage; a second clock generation unit configured to output a second signal which swings between the level of the set voltage and a level of a ground voltage; and a regulator configured to supply the set voltage to the first clock generation unit and the second clock generation unit.
摘要翻译：半导体装置的时钟产生电路包括：第一时钟生成单元，被配置为输出在电源电压的电平和设定电压的电平之间摆动的第一信号; 第二时钟生成单元，被配置为输出在所述设定电压的电平和接地电压的电平之间摆动的第二信号; 以及调节器，被配置为将设定电压提供给第一时钟生成单元和第二时钟生成单元。

2. 发明授权

US08854912B2 Semiconductor module including module control circuit and method for controlling the same 有权
标题翻译：半导体模块包括模块控制电路及其控制方法
公开(公告)号：US08854912B2
公开(公告)日：2014-10-07
申请号：US13738492
申请日：2013-01-10
申请人： SK hynix Inc.
发明人： Ki Han Kim , Hyun Woo Lee
IPC分类号： G11C8/00 , G11C5/02 , H03K3/02
CPC分类号： H03K3/02 , G11C5/02
摘要： A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal.
摘要翻译：模块控制电路包括：输入单元，被配置为从多个数据输入/输出引脚接收多个数据信号，并输出识别信号和内部命令信号。闩锁单元被配置为根据第一使能信号锁定识别信号以输出第一组识别信号，根据第二使能信号锁存识别信号以输出第二组识别信号，并锁存内部命令信号根据第二使能信号输出组指令信号。比较器被配置为将第一组识别信号与第二组识别信号进行比较，并产生选择信号。复用器被配置为响应于选择信号选择组命令信号和模块命令信号之一作为输入命令。

3. 发明授权

US11372563B2 Storage device and operating method thereof 有权
公开(公告)号：US11372563B2
公开(公告)日：2022-06-28
申请号：US16549437
申请日：2019-08-23
申请人： SK hynix Inc.
发明人： Hyun Woo Lee , Young Gyun Kim
IPC分类号： G06F3/06 , G06F12/02
摘要： A storage device having an improved operation speed includes a memory controller for controlling a memory device. The memory controller includes a parameter data generator for generating parameter data for changing a parameter value related to an operation of the memory device, and a parameter controller for outputting the parameter data. The parameter data includes an error protection field associated with the parameter value.

4. 发明授权

US11327839B2 Storage device and method of operating the same 有权
公开(公告)号：US11327839B2
公开(公告)日：2022-05-10
申请号：US17006062
申请日：2020-08-28
申请人： SK hynix Inc.
发明人： Hyun Woo Lee
IPC分类号： G06F11/10 , G06F3/06 , G11C16/26 , G11C16/04
摘要： The present technology relates to an electronic device. According to the present technology, a storage device having improved original data recovery capability may include a memory device including a plurality of memory cells, and configured to perform a read operation on data stored in the plurality of memory cells according to read mode information, and to output read data associated with the read operation and a memory controller configured to receive the read data, change the read mode information when error correction decoding for the read data fails, and control the memory device to perform the read operation again according to the changed read mode information. The read mode information may include information on a data interface between the memory device and the memory controller.

5. 发明授权

US10128844B2 Semiconductor apparatus and reduced current and power consumption 有权
公开(公告)号：US10128844B2
公开(公告)日：2018-11-13
申请号：US14847285
申请日：2015-09-08
申请人： SK hynix Inc.
发明人： Hyun Woo Lee
IPC分类号： H03K19/00 , H03K19/08 , H03K3/012 , H03K3/356 , H03K19/094
摘要： A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.

6. 发明授权

US09373381B2 System including memories sharing calibration reference resistor and calibration method thereof 有权
标题翻译：系统包括共享校准参考电阻的存储器及其校准方法
公开(公告)号：US09373381B2
公开(公告)日：2016-06-21
申请号：US14487605
申请日：2014-09-16
申请人： SK hynix Inc.
发明人： Hyun Woo Lee
IPC分类号： G11C7/06 , G11C8/18 , G11C7/14 , G11C29/02 , G11C29/50
CPC分类号： G11C8/18 , G11C7/1057 , G11C7/1084 , G11C7/14 , G11C7/222 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： A semiconductor apparatus includes a first memory, a second memory, and a shared reference resistor. The first memory is electrically coupled to the shared reference resistor, and the second memory is also electrically coupled to the shared reference resistor. Each of the first and second memories performs a basic calibration operation thereof by selectively using the shared reference resistor in response to a clock signal, and a mirror function signal, which has different logic levels according to which memory between the first and second memories performs calibration operations.
摘要翻译：半导体装置包括第一存储器，第二存储器和共享参考电阻器。第一存储器电耦合到共享参考电阻器，并且第二存储器也电耦合到共享参考电阻器。第一和第二存储器中的每一个通过选择性地使用共享参考电阻器响应于时钟信号执行其基本校准操作，以及镜像功能信号，其根据第一和第二存储器之间的存储器执行校准具有不同的逻辑电平操作。

7. 发明授权

US09160335B2 Semiconductor apparatus and reduced current and power consumption 有权
标题翻译：半导体装置，降低电流和功耗
公开(公告)号：US09160335B2
公开(公告)日：2015-10-13
申请号：US14190372
申请日：2014-02-26
申请人： SK hynix Inc.
发明人： Hyun Woo Lee
IPC分类号： H04L1/00 , H03K19/00 , H03K3/012 , H03K3/356 , H03K19/094
CPC分类号： H03K19/0008 , H03K3/012 , H03K3/356034 , H03K19/0013 , H03K19/08 , H03K19/09436
摘要： A semiconductor apparatus may include a mode control circuit configured to output differential output signals which swing in a current mode logic (CML) area and a first control signal, in response to a power-down mode signal; a first circuit unit configured to be provided with the differential output signals, and operate in a power-down mode; and a second circuit unit configured to be provided with the differential output signals, and be interrupted in its operation in the power-down mode.
摘要翻译：半导体装置可以包括模式控制电路，其被配置为响应于掉电模式信号而输出在电流模式逻辑（CML）区域和第一控制信号中摆动的差分输出信号; 第一电路单元，被配置为提供差分输出信号，并以断电模式操作; 以及第二电路单元，被配置为提供差分输出信号，并且在断电模式下在其操作中被中断。

8. 发明授权

US09236108B1 Semiconductor memory apparatus 有权
标题翻译：半导体存储装置
公开(公告)号：US09236108B1
公开(公告)日：2016-01-12
申请号：US14526082
申请日：2014-10-28
申请人： SK hynix Inc.
发明人： Soo Young Jang , Hyun Woo Lee
IPC分类号： G11C7/10 , G11C11/406 , G11C11/4063
CPC分类号： G11C11/40618 , G11C11/4087 , G11C11/4094
摘要： A semiconductor memory apparatus may include a row address control block configured to output an address as a row address or output a counted signal as the row address in response to a refresh signal and the address, and generate an auto-precharge signal and a pre-bank active signal in response to the refresh signal and a bank active signal. The semiconductor memory apparatus may include a bank control block configured to generate the bank active signal in response to an active signal, a precharge signal, a bank address signal, the auto-precharge signal and the pre-bank active signal.
摘要翻译：半导体存储装置可以包括行地址控制块，其被配置为响应于刷新信号和地址而将地址作为行地址输出或输出计数信号作为行地址，并且生成自动预充电信号和预置信号，响应于刷新信号和存储体活动信号的存储体活动信号。半导体存储装置可以包括存储体控制块，其被配置为响应于有效信号，预充电信号，存储体地址信号，自动预充电信号和预存储器活动信号来产生存储体有效信号。

9. 发明授权

US10969987B2 Memory device, memory system including the memory device, and method of operating the memory system 有权
公开(公告)号：US10969987B2
公开(公告)日：2021-04-06
申请号：US16395890
申请日：2019-04-26
申请人： SK hynix Inc.
发明人： Hyun Woo Lee , Young Gyun Kim
IPC分类号： G06F3/06 , G06F11/10 , G11C29/52 , G11C16/34 , G06F12/02 , G11C11/56 , G11C16/26 , G11C13/00 , G11C16/16
摘要： A memory system includes: a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform a read operation on a selected memory block among the plurality of memory blocks and a backup program operation on a backup block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit to backup data of logical pages included in the selected memory block in the backup block, when a read count of a selected physical page of the selected memory block is equal to or larger than a set value in the read operation on the selected memory block.

10. 发明授权

US10831406B2 Memory controller, memory system having the same, and method of operating the same 有权
公开(公告)号：US10831406B2
公开(公告)日：2020-11-10
申请号：US16184328
申请日：2018-11-08
申请人： SK hynix Inc.
发明人： Hyun Woo Lee
IPC分类号： G06F3/06 , G11C29/38 , G11C29/14 , G11C16/04
摘要： A memory controller includes an interleaving component configured to determine an access sequence of a plurality of memory units based on estimated execution times for the respective memory units to perform an operation, and a processor configured to access the memory units in the determined access sequence to perform the operation in an interleaved manner.

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