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1. 发明授权

US08756442B2 System for processor power limit management 有权
标题翻译：处理器功率限制管理系统
公开(公告)号：US08756442B2
公开(公告)日：2014-06-17
申请号：US12970172
申请日：2010-12-16
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati , William A. Hughes
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati , William A. Hughes
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a power dissipation due to processor load. A power controller is configured to adjust a processor power parameter based on the power target and the power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the power dissipation stays below the processor power target, software processor power target and the agent processor power target.
摘要翻译：提供了一种处理器功率限制器和方法。处理器包括被配置为存储处理器功率目标的第一可编程位置。功率监视器配置为估计由于处理器负载引起的功耗。功率控制器被配置为基于功率目标和功率消耗来调整处理器功率参数。处理器可以包括用于操作系统的接口。可以将第二可编程位置配置为存储由操作系统可访问的软件处理器功率目标。处理器还可以包括用于外部代理的边带接口。可以将第三可编程位置配置为存储由外部代理可访问的代理处理器功率目标。功率控制器可以被配置为调整处理器核心电压和/或频率，使得功率消耗保持在处理器功率目标，软件处理器功率目标和代理处理器功率目标之下。

2. 发明申请

US20120159198A1 PROCESSOR POWER LIMIT MANAGEMENT 有权
标题翻译：处理器功率限制管理
公开(公告)号：US20120159198A1
公开(公告)日：2012-06-21
申请号：US12970172
申请日：2010-12-16
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a measured power dissipation within the processor. A power controller is configured to adjust a processor power parameter based on the power target and the measured power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the measured dissipation stays below the processor power target, software processor power target and the agent processor power target.
摘要翻译：提供了一种处理器功率限制器和方法。处理器包括被配置为存储处理器功率目标的第一可编程位置。功率监视器被配置为估计处理器内的测量功率耗散。功率控制器被配置为基于功率目标和测量的功率耗散来调整处理器功率参数。处理器可以包括用于操作系统的接口。可以将第二可编程位置配置为存储由操作系统可访问的软件处理器功率目标。处理器还可以包括用于外部代理的边带接口。可以将第三可编程位置配置为存储由外部代理可访问的代理处理器功率目标。功率控制器可以被配置为调整处理器核心电压和/或频率，使得所测量的功率保持在处理器功率目标，软件处理器功率目标和代理处理器功率目标之下。

3. 发明申请

US20120144215A1 MAXIMUM CURRENT LIMITING METHOD AND APPARATUS 审中-公开
标题翻译：最大电流限制方法和装置
公开(公告)号：US20120144215A1
公开(公告)日：2012-06-07
申请号：US12960095
申请日：2010-12-03
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , Y02D10/126
摘要： The maximum current is limited in a multi-processor core system by monitoring the latest power consumption in the processor cores, in order to prevent a system shutdown as a result of an over-current event. If the sum of the latest power of the processor cores exceeds a threshold limit, a performance state (P-state) limit is enforced in the processor cores. The P-state limit causes a P-state change to a lower frequency, voltage and thus a lower current.
摘要翻译：通过监控处理器核心中的最新功耗，多处理器核心系统中的最大电流受到限制，以防止由于过电流事件导致系统关闭。如果处理器核心的最新功率的总和超过阈值限制，则在处理器核心中执行性能状态（P状态）限制。 P态极限导致P态变化到较低的频率，电压，从而导致较低的电流。

4. 发明授权

US09182803B2 Load step mitigation method and apparatus 有权
标题翻译：负载阶梯缓解方法和装置
公开(公告)号：US09182803B2
公开(公告)日：2015-11-10
申请号：US12958533
申请日：2010-12-02
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152
摘要： A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation.
摘要翻译：提供了用于负载阶跃或瞬时电流尖峰的方法和装置。在该方法和装置中，如果计算机系统整体轻负载，则可以减轻负载阶跃，这可以由计算机系统的功耗确定。此外，如果能够引起负载阶跃的多个处理器核心高于阈值，则减轻负载步骤。内核的高级配置和电源接口（ACPI）性能状态用于确定内核生成加载步骤的可能性。如果满足缓解条件，则指示处理器内核减轻负载步骤。

5. 发明申请

US20120159123A1 CSTATE BOOST METHOD AND APPARATUS 审中-公开
标题翻译： CSTATE BOOST方法和装置
公开(公告)号：US20120159123A1
公开(公告)日：2012-06-21
申请号：US12971734
申请日：2010-12-17
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
IPC分类号： G06F9/32
CPC分类号： G06F1/3243 , G06F9/5094 , Y02D10/152 , Y02D10/22
摘要： A central processing unit (processor) having multiple cores and a method for controlling the performance of the processor. The processor includes a first storage location configured to store a first threshold associated with a first boost performance state (P-State). The processor also includes logic circuitry configured to increase performance of active processor cores when an inactive processor core count meets or exceeds the first threshold. The processor may also include a second storage location configured to store a second threshold associated with a second boost P-State. The logic circuitry may be configured to compare the inactive processor core count to the first and second thresholds, select one of the first and second boost P-States and increase performance of active processor cores based on the selected boost P-State.
摘要翻译：具有多个核的中央处理单元（处理器）和用于控制处理器性能的方法。处理器包括被配置为存储与第一升压性能状态（P状态）相关联的第一阈值的第一存储位置。处理器还包括配置成当非活动处理器核心计数满足或超过第一阈值时增加主动处理器核心的性能的逻辑电路。处理器还可以包括被配置为存储与第二升压P状态相关联的第二阈值的第二存储位置。逻辑电路可以被配置为将非活动处理器核心计数与第一和第二阈值进行比较，选择第一和第二升压P状态中的一个，并且基于所选择的升压P状态增加主动处理器核的性能。

6. 发明申请

US20120144221A1 LOAD STEP MITIGATION METHOD AND APPARATUS 有权
标题翻译：负载减速方法和装置
公开(公告)号：US20120144221A1
公开(公告)日：2012-06-07
申请号：US12958533
申请日：2010-12-02
申请人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
发明人： Samuel D. Naffziger , John P. Petry , Kiran Bondalapati
IPC分类号： G06F1/26 , G06F9/30
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152
摘要： A method and apparatus for load step, or instantaneous current spike, mitigation are provided. In the method and apparatus, load steps are mitigated if a computer system a whole is lightly load, which may be determined by the power consumption of the computer system. Further, load steps are mitigated if a number of processor cores capable of inducing a load step is higher than a threshold. The Advanced Configuration and Power Interface (ACPI) performance state of the cores is used to determine a core's potential for generating a load step. A processor core is instructed to mitigate load steps if conditions are met for the mitigation.
摘要翻译：提供了用于负载阶跃或瞬时电流尖峰的方法和装置。在该方法和装置中，如果计算机系统整体轻负载，则可以减轻负载阶跃，这可以由计算机系统的功耗确定。此外，如果能够引起负载阶跃的多个处理器核心高于阈值，则减轻负载步骤。内核的高级配置和电源接口（ACPI）性能状态用于确定内核生成加载步骤的可能性。如果满足缓解条件，则指示处理器内核减轻负载步骤。

7. 发明申请

US20110301889A1 FLEXIBLE POWER REPORTING IN A COMPUTING SYSTEM 有权
标题翻译：计算机系统中的灵活电力报告
公开(公告)号：US20110301889A1
公开(公告)日：2011-12-08
申请号：US12792308
申请日：2010-06-02
申请人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
发明人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
IPC分类号： G01R21/00 , G05D23/19 , G06F19/00
CPC分类号： G06F1/3203 , G06F1/206 , H05K7/20836 , Y02D10/16
摘要： A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on data corresponding to activity levels of one or more functional blocks within the processor. This data corresponds to each of a number of sampled signals within the one or more functional blocks rather than temperature. Thus, the data is independent of environment temperature variations. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent, such as a controller for a data center rack system. Responsive to receiving and processing the average power consumption number, the external agent may perform one or more actions. For example, the external agent may cause changes in a cooling system.
摘要翻译：一种有效报告电力使用的系统和方法。处理器内的电力报告单元从功率监视器接收每个采样间隔一次的功耗数字。功率监视器基于与处理器内的一个或多个功能块的活动级别对应的数据来确定功耗数量。该数据对应于一个或多个功能块内的多个采样信号中的每个，而不是温度。因此，数据与环境温度变化无关。基于运行时间间隔的接收功耗数来计算平均功耗数，其中运行时间间隔大于采样间隔。该值被传送到外部代理，例如用于数据中心机架系统的控制器。响应于接收和处理平均功耗数量，外部代理可以执行一个或多个动作。例如，外部代理可能导致冷却系统的变化。

8. 发明授权

US08612781B2 Method and apparatus for application of power density multipliers optimally in a multicore system 有权
标题翻译：在多核系统中最佳应用功率密度乘法器的方法和装置
公开(公告)号：US08612781B2
公开(公告)日：2013-12-17
申请号：US12967535
申请日：2010-12-14
申请人： Samuel D. Naffziger , John P. Petry , Sridhar Sundaram
发明人： Samuel D. Naffziger , John P. Petry , Sridhar Sundaram
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3287 , Y02D10/16 , Y02D10/171
摘要： A method and an apparatus are described that delay application of a higher order Power Density Multiplier (PDM) using a time based moving average of a number of active cores in a multicore system. A PDM is applied to a thermal design power budget of a thermal entity and performance of the thermal entity is increased by transferring available power from a thermal entity not in an active state to a thermal entity in an active state. Sufficient time is allowed for the cooling effect of reduced active cores, to influence the active core that receives the extra power (a higher PDM). Similarly delaying application of a lower PDM with the same moving average, but a different threshold, allows a core to retain a higher power allocation until the more active neighbor core(s) cause it to heat up, thereby boosting core performance.
摘要翻译：描述了使用多核系统中的多个活动核心的基于时间的移动平均来延迟应用较高阶功率密度乘数（PDM）的方法和装置。将PDM应用于热实体的热设计功率预算，并且通过将来自不处于活动状态的热实体的可用功率传递到处于活动状态的热实体的可用功率来增加热实体的性能。允许减少活动核心的冷却效果足够的时间来影响接收额外功率的有源核心（较高的PDM）。类似地延迟具有相同移动平均值但是不同阈值的较低PDM的应用允许核心保持较高的功率分配，直到较活跃的相邻核心使其升温，从而提高核心性能。

9. 发明授权

US08504854B2 Managing multiple operating points for stable virtual frequencies 有权
标题翻译：为稳定的虚拟频率管理多个操作点
公开(公告)号：US08504854B2
公开(公告)日：2013-08-06
申请号：US12819777
申请日：2010-06-21
申请人： Samuel D. Naffziger , John P. Petry , William A. Hughes
发明人： Samuel D. Naffziger , John P. Petry , William A. Hughes
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.
摘要翻译：一种用于管理多个离散工作点以创建稳定的虚拟操作点的系统和方法。处理器内的一个或多个功能块产生对应于与相应功能块相关联的活动级别的数据。功率管理器基于每个给定采样间隔一次的数据来确定功耗值。此外，功率管理器确定在热设计功率（TDP）和功耗值之间随时间的经签名的积分差。功率管理器基于签名累积差和给定阈值的比较来选择下一个功率性能状态（P状态）。以这种方式在P状态之间转换，而工作负载不会显着变化，导致处理器在支持的离散工作点之间的虚拟工作点运行。

10. 发明授权

US08442786B2 Flexible power reporting in a computing system 有权
标题翻译：计算系统中灵活的电力报告
公开(公告)号：US08442786B2
公开(公告)日：2013-05-14
申请号：US12792308
申请日：2010-06-02
申请人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
发明人： Samuel D. Naffziger , John P. Petry , Kiran K. Bondalapati , Mom-Eng Ng
IPC分类号： G01R21/00 , G06F1/00
CPC分类号： G06F1/3203 , G06F1/206 , H05K7/20836 , Y02D10/16
摘要： A system and method for efficient reporting of power usage. A power reporting unit within a processor receives a power consumption number once every sample interval from a power monitor. The power monitor determines a power consumption number based on sampled signals within one or more functional blocks in the processor, rather than based on temperature. An average power consumption number is computed based on received power consumption numbers for a running time interval, wherein the running time interval is larger than the sample interval. This value is conveyed to an external agent. Responsive to receiving and processing the average power consumption number, the external agent may cause changes in a cooling system.
摘要翻译：一种有效报告电力使用的系统和方法。处理器内的电力报告单元从功率监视器接收每个采样间隔一次的功耗数字。功率监视器基于处理器中的一个或多个功能块内的采样信号而不是基于温度来确定功耗数。基于运行时间间隔的接收功耗数来计算平均功耗数，其中运行时间间隔大于采样间隔。该值传送给外部代理。响应于接收和处理平均功耗数量，外部代理可能导致冷却系统的变化。

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