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1. 发明授权

US09564226B1 Smart verify for programming non-volatile memory 有权
标题翻译：智能验证用于编程非易失性存储器
公开(公告)号：US09564226B1
公开(公告)日：2017-02-07
申请号：US14928436
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Mohan Dunga , Gerrit Jan Hemink , Zhenming Zhou , Masaaki Higashitani
IPC分类号： G11C11/34 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/3459
摘要： Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By applying the smart verify to just a subset of the memory cells current is saved. The smart verify may be used to characterize programming speed. Results of the smart verify may be used to determine a magnitude of a dummy program pulse to be applied later in the programming process. The dummy program pulse is not followed by a program verify, which reduces current. If the dummy program pulse pushes threshold voltages high enough, then those memory cells will not conduct a current when verifying later in programming. Thus, current is saved during the program verify. Also, bit lines of memory cells that received the dummy pulses do not need to be pre-charged prior to a program pulse, which can save more current.
摘要翻译：提供了在编程非易失性存储时减少电流消耗的技术。使用存储器单元的子集执行智能验证。通过将智能验证应用到存储器单元的一个子集，保存当前的电流。智能验证可用于表征编程速度。可以使用智能验证的结果来确定在编程过程中稍后应用的虚拟编程脉冲的幅度。虚拟程序脉冲不在程序验证后面，这样可以减少电流。如果虚拟程序脉冲将阈值电压推到足够高的位置，那么当编程稍后验证时，这些存储单元将不会导通电流。因此，在程序验证期间保存电流。此外，接收到伪脉冲的存储单元的位线在编程脉冲之前不需要被预充电，这可以节省更多的电流。

2. 发明授权

US09355713B2 Systems and methods for lower page writes 有权
标题翻译：较低页面写入的系统和方法
公开(公告)号：US09355713B2
公开(公告)日：2016-05-31
申请号：US14528892
申请日：2014-10-30
申请人： SanDisk Technologies Inc.
发明人： Jianmin Huang , Bo Lei , Jun Wan , Gerrit Jan Hemink , Steven T. Sprouse , Dana Lee
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C2211/5641
摘要： In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
摘要翻译：在多级单元（MLC）存储器阵列块中，首先写入低层页面，在任何高层页面之前，下层数据进行异或（XOR）操作，以便如果任何下层页面由ECC（UECC）无法校正），则可以使用XOR恢复页面。这些块中的下页可以以非顺序的顺序写入。

3. 发明申请

US20150043281A1 NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION BASED ON NEIGHBOR STATE INFORMATION 有权
标题翻译：基于邻国状态信息的温度补偿非挥发性储存
公开(公告)号：US20150043281A1
公开(公告)日：2015-02-12
申请号：US14524238
申请日：2014-10-27
申请人： SANDISK TECHNOLOGIES INC.
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642
摘要： Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.
摘要翻译：数据被编程到一组目标存储器单元中并从其读取。读取数据时，提供温度补偿。温度补偿基于温度信息和一个或多个相邻存储单元的状态。在一个实施例中，当从目标存储器单元的集合读取数据时，系统感测当前温度并确定当前温度与数据编程时的温度之间的温度差。如果温度差大于阈值，则读取数据的过程包括基于温度信息和邻近状态信息提供温度补偿。在一个替代方案中，提供温度补偿的决定可以由温差以外的条件触发。

4. 发明授权

US08902652B1 Systems and methods for lower page writes 有权
标题翻译：较低页面写入的系统和方法
公开(公告)号：US08902652B1
公开(公告)日：2014-12-02
申请号：US14276925
申请日：2014-05-13
申请人： SanDisk Technologies Inc.
发明人： Jianmin Huang , Bo Lei , Jun Wan , Gerrit Jan Hemink , Steven T. Sprouse , Dana Lee
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5642 , G11C16/0483 , G11C2211/5641
摘要： In a Multi Level Cell (MLC) memory array block in which lower pages are written first, before any upper pages, the lower page data is subject to an exclusive OR (XOR) operation so that if any lower page becomes uncorrectable by ECC (UECC) then the page can be recovered using XOR. Lower pages in such blocks may be written in nonsequential order.
摘要翻译：在多级单元（MLC）存储器阵列块中，首先写入低层页面，在任何高层页面之前，下层数据进行异或（XOR）操作，以便如果任何下层页面由ECC（UECC）无法校正），则可以使用XOR恢复页面。这些块中的下页可以以非顺序的顺序写入。

5. 发明授权

US08605513B2 Detecting the completion of programming for non-volatile storage 有权
公开(公告)号：US08605513B2
公开(公告)日：2013-12-10
申请号：US13622230
申请日：2012-09-18
申请人： SanDisk Technologies Inc.
发明人： Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level.

6. 发明授权

US09502471B1 Multi tier three-dimensional memory devices including vertically shared bit lines 有权
标题翻译：包括垂直共享位线的多层三维存储器件
公开(公告)号：US09502471B1
公开(公告)日：2016-11-22
申请号：US14834943
申请日：2015-08-25
申请人： SANDISK TECHNOLOGIES INC.
发明人： Zhenyu Lu , Henry Chien , Johann Alsmeier , Koji Miyata , Tong Zhang , Man Mui , James Kai , Wenguang Shi , Wei Zhao , Xiaolong Hu , Jiyin Xu , Gerrit Jan Hemink , Christopher Petti
IPC分类号： H01L47/00 , H01L27/24 , H01L27/115 , H01L23/528 , H01L23/522 , H01L29/788 , H01L45/00 , H01L29/66 , H01L21/768
CPC分类号： H01L23/528 , H01L21/768 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66666 , H01L29/7883 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.
摘要翻译：多层存储器件形成在衬底上，使得存储器堆叠结构延伸穿过绝缘层的交替堆叠和每层内的导电层。位线形成在具有半导体通道上的漏极区域的底层和在半导体通道下方具有漏极区域的上层，使得位线在下层和上覆层之间共享。可以在每个层上形成源极线，其中源极区域覆盖半导体沟道和漏极区域。如果源线上方存在另一层，则可以在两个垂直相邻层之间共享源线。

7. 再颁专利

USRE45871E1 Selected word line dependent select gate voltage during program 有权
标题翻译：程序中所选字线相关选择栅极电压
公开(公告)号：USRE45871E1
公开(公告)日：2016-01-26
申请号：US14284163
申请日：2014-05-21
申请人： SanDisk Technologies Inc.
发明人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
IPC分类号： G11C11/34 , G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。这可以是源极侧或漏极侧选择晶体管。这可能会阻止或减少由于DIBL而导致的程序干扰。这也可以防止或减少由于GIDL可能导致的程序干扰。当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

8. 再颁专利

USRE45754E1 Selective memory cell program and erase 有权
标题翻译：选择性存储单元程序和擦除
公开(公告)号：USRE45754E1
公开(公告)日：2015-10-13
申请号：US14226276
申请日：2014-03-26
申请人： SanDisk Technologies Inc.
发明人： Yingda Dong , Tien-chien Kuo , Gerrit Jan Hemink
IPC分类号： G11C16/04 , G11C11/56 , G11C16/10 , G11C16/30 , G11C16/16 , G11C16/14
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C2211/5641
摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.
摘要翻译：本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。之后，只有奇数字线被编程。数据可以被传送到在擦除之前存储多个存储单元的位的块。在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

9. 发明授权

US08644075B2 Ramping pass voltage to enhance channel boost in memory device 有权
标题翻译：缓存通过电压以增强存储器件中的通道升压
公开(公告)号：US08644075B2
公开(公告)日：2014-02-04
申请号：US13955597
申请日：2013-07-31
申请人： SanDisk Technologies Inc.
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的第一和第二衬底沟道区在编程期间被增强以抑制编程干扰。第一和第二衬底沟道区域在隔离字线的任一侧上产生。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到直接在第二通道区域上延伸的未选择字线的电压以更快的速度升高到相应的预编程脉冲电压施加到直接在第一通道区域上延伸的未选择字线的电压的速率被升高到相应的预编程脉冲电压。这有助于改善通道区域之间的隔离。

10. 再颁专利

USRE46264E1 Verification process for non-volatile storage 有权
标题翻译：非易失性存储的验证过程
公开(公告)号：USRE46264E1
公开(公告)日：2017-01-03
申请号：US14290905
申请日：2014-05-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Toru Miwa , Yupin Fong , Jun Wan , Ken Oowada
IPC分类号： G11C16/06 , G11C16/34
CPC分类号： G11C16/3418
摘要： When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.
摘要翻译：当擦除非易失性存储时，在擦除操作之间使用验证过程来确定非易失性存储器是否已被成功擦除。验证过程包括对非易失性存储元件的不同子集进行单独执行验证。

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