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1. 发明申请

US20070066083A1 Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same 有权
标题翻译：通过原子层沉积工艺形成富硅纳米晶体结构的方法和使用其制造非易失性半导体器件的方法
公开(公告)号：US20070066083A1
公开(公告)日：2007-03-22
申请号：US11494451
申请日：2006-07-28
申请人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
发明人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
IPC分类号： H01L21/31 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/02164 , B82Y10/00 , C23C16/308 , C23C16/401 , C23C16/45529 , H01L21/0214 , H01L21/02211 , H01L21/0228 , H01L21/02337 , H01L21/28273 , H01L21/3141 , H01L21/32055 , H01L29/42328 , Y10S438/962
摘要： In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.
摘要翻译：在通过ALD工艺形成富含硅的纳米晶体结构的方法中，将包含第一硅化合物的第一气体提供到物体上以在物体上形成富含硅的化学吸附层。在富含硅的化学吸附层上提供包含氧的第二气体，以在物体上形成富含硅的绝缘层。在富硅绝缘层上提供包括第二硅化合物的第三气体，以在富硅绝缘层上形成硅纳米晶层。可以重复地提供第一气体，第二气体和第三气体以交替地形成在物体上具有多个富硅绝缘层和多个硅纳米晶层的富含硅的纳米晶体结构。

2. 发明授权

US07419888B2 Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same 有权
标题翻译：通过原子层沉积工艺形成富硅纳米晶体结构的方法和使用其制造非易失性半导体器件的方法
公开(公告)号：US07419888B2
公开(公告)日：2008-09-02
申请号：US11494451
申请日：2006-07-28
申请人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
发明人： Sang-Ryol Yang , Kyong-Hee Joo , In-Seok Yeo , Ki-Hyun Hwang , Seung-Hyun Lim
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02164 , B82Y10/00 , C23C16/308 , C23C16/401 , C23C16/45529 , H01L21/0214 , H01L21/02211 , H01L21/0228 , H01L21/02337 , H01L21/28273 , H01L21/3141 , H01L21/32055 , H01L29/42328 , Y10S438/962
摘要： In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.
摘要翻译：在通过ALD工艺形成富含硅的纳米晶体结构的方法中，将包含第一硅化合物的第一气体提供到物体上以在物体上形成富含硅的化学吸附层。在富含硅的化学吸附层上提供包含氧的第二气体，以在物体上形成富含硅的绝缘层。在富硅绝缘层上提供包括第二硅化合物的第三气体，以在富硅绝缘层上形成硅纳米晶层。可以重复地提供第一气体，第二气体和第三气体以交替地形成在物体上具有多个富硅绝缘层和多个硅纳米晶层的富含硅的纳米晶体结构。

3. 发明申请

US20110045667A1 Gate of a transistor and method of forming the same 审中-公开
标题翻译：晶体管的栅极及其形成方法
公开(公告)号：US20110045667A1
公开(公告)日：2011-02-24
申请号：US12926151
申请日：2010-10-28
申请人： Jin-Gyun Kim , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Jin-Gyun Kim , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/28
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/823456 , H01L21/82385
摘要： A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.
摘要翻译：晶体管的栅极包括形成在半导体器件上的栅极氧化层，包含掺杂有硼的多晶硅并形成在栅极氧化物层上的第一导电层图案，包括通过化学气相沉积工艺形成的非晶硅的扩散防止层图案，其使用形成在第一导电层图案上的具有丙硅烷（Si 3 H 8）的反应气体和形成在扩散防止层图案上的包含金属硅化物的第二导电层图案。由于PMOS晶体管的栅极包括具有优异表面形态的扩散防止层，因此充分防止了杂质的扩散。因此，可以降低PMOS晶体管的阈值电压，并且可以提高阈值电压分布。

4. 发明申请

US20120115293A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120115293A1
公开(公告)日：2012-05-10
申请号：US13287509
申请日：2011-11-02
申请人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae NOH , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/336 , H01L21/8234 , B82Y40/00
CPC分类号： H01L27/1157 , H01L27/10855 , H01L27/11582
摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
摘要翻译：在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。绝缘夹层包括与牺牲层的材料不同的材料。通过绝缘夹层和牺牲层形成至少一个开口。至少一个开口露出基板。种子层使用第一硅源气体形成在至少一个开口的内壁上。通过种植种子层在至少一个开口中形成多晶硅沟道。去除牺牲层以在绝缘夹层之间形成多个凹槽。在槽中分别形成有多个栅极结构。

5. 发明授权

US07510935B2 Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device 有权
标题翻译：电荷俘获电介质的制造方法和声波型非易失性半导体器件的制造方法
公开(公告)号：US07510935B2
公开(公告)日：2009-03-31
申请号：US11468944
申请日：2006-08-31
申请人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Sang-Ryol Yang , Ki-Hyun Hwang
发明人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Sang-Ryol Yang , Ki-Hyun Hwang
IPC分类号： H01L21/8247
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , Y10S438/954
摘要： In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.
摘要翻译：在一个实施例中，制造电荷俘获电介质和氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体器件的方法包括形成电荷俘获电介质和包含氧化硅的第一氧化物层。通过使用硅源材料和氮源气体的循环化学气相沉积（CVD）工艺形成包括富含硅的氮化物的氮化硅层。在氮化硅层上形成第二氧化物层。因此，形成具有良好擦除特性的电荷俘获电介质。在包含电荷捕获电介质的SONOS型非易失性半导体器件中，可以稳定地执行数据擦除处理。

6. 发明授权

US07951671B2 Method of fabricating non-volatile memory device having separate charge trap patterns 失效
标题翻译：制造具有单独的电荷陷阱图案的非易失性存储器件的方法
公开(公告)号：US07951671B2
公开(公告)日：2011-05-31
申请号：US12453419
申请日：2009-05-11
申请人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/78 , H01L29/7851 , H01L29/792
摘要： A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.
摘要翻译：一种制造非易失性存储器件的方法包括在半导体衬底中形成隔离沟槽，隔离沟槽限定第一和第二鳍片。该方法还包括形成部分地填充隔离沟槽的隔离层，分别形成分别覆盖从隔离层突出的第一和第二鳍片的部分的第一和第二电荷陷阱图案，以及形成覆盖第一和第二电荷陷阱图案的控制栅电极并穿过第一和第二鳍片。

7. 发明申请

US20070042548A1 Methods of forming floating gates in non-volatile memory devices including alternating layers of amorphous silicon and ALD dopant layers and floating gates so formed 审中-公开
标题翻译：在非易失性存储器件中形成浮置栅极的方法包括如此形成的非晶硅和ALD掺杂剂层的交替层和浮置栅极
公开(公告)号：US20070042548A1
公开(公告)日：2007-02-22
申请号：US11496177
申请日：2006-07-31
申请人： Jin-Tae Noh , Ki-Hyun Hwang , Jae-Young Ahn , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae Noh , Ki-Hyun Hwang , Jae-Young Ahn , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/157 , H01L27/115 , H01L27/11521
摘要： A method of forming a silicon layer on a substrate includes providing a silicon source gas to form an amorphous silicon layer on a substrate and providing a dopant source gas to adsorb dopants onto the amorphous silicon layer to form a dopant layer on a surface of the amorphous silicon layer. Related floating gates are also disclosed.
摘要翻译：在衬底上形成硅层的方法包括提供硅源气体以在衬底上形成非晶硅层，并提供掺杂剂源气体以将掺杂剂吸附到非晶硅层上以在无定形的表面上形成掺杂剂层硅层。相关浮动门也被披露。

8. 发明申请

US20090072294A1 Method of manufacturing a non-volatile memory device 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090072294A1
公开(公告)日：2009-03-19
申请号：US11974636
申请日：2007-10-15
申请人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
发明人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the tunnel oxide layer using a trisilane (Si3H8) gas as a silicon source gas. The tunnel oxide layer and the polysilicon layer are then patterned into a tunnel oxide layer pattern and a polysilicon layer pattern, respectively. A dielectric layer and a conductive layer corresponding to a control gate are subsequently formed on the polysilicon layer pattern. The polysilicon layer is formed using trisilane (Si3H8) gas as a result of which the polysilicon layer may be formed to have a relatively thin thickness while maintaining a thickness uniformity and realizing a superior morphology thus producing a floating gate having enhanced performance.
摘要翻译：公开了一种使用相对薄的多晶硅层作为浮动栅极的非易失性存储器件的制造方法，其中在衬底上形成隧道氧化物层，然后形成厚度为约至大约的厚度的多晶硅层使用丙硅烷（Si 3 H 8）气体作为硅源气体在隧道氧化物层上形成。然后将隧道氧化物层和多晶硅层分别图案化为隧道氧化物层图案和多晶硅层图案。随后在多晶硅层图案上形成对应于控制栅的电介质层和导电层。使用丙硅烷（Si 3 H 8）气体形成多晶硅层，结果可以形成多晶硅层以具有相对较薄的厚度，同时保持厚度均匀性并实现优异的形态，从而产生具有增强性能的浮栅。

9. 发明授权

US08445367B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08445367B2
公开(公告)日：2013-05-21
申请号：US13287509
申请日：2011-11-02
申请人： Jin-Tae Noh , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
发明人： Jin-Tae Noh , Hun-Hyeong Lim , Ki-Hyun Hwang , Jin-Gyun Kim , Sang-Ryol Yang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L27/1157 , H01L27/10855 , H01L27/11582
摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.
摘要翻译：在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。绝缘夹层包括与牺牲层的材料不同的材料。通过绝缘夹层和牺牲层形成至少一个开口。至少一个开口露出基板。种子层使用第一硅源气体形成在至少一个开口的内壁上。通过种植种子层在至少一个开口中形成多晶硅沟道。去除牺牲层以在绝缘夹层之间形成多个凹槽。在槽中分别形成有多个栅极结构。

10. 发明申请

US20090221140A1 Method of fabricating non-volatile memory device having separate charge trap patterns 失效
标题翻译：制造具有单独的电荷陷阱图案的非易失性存储器件的方法
公开(公告)号：US20090221140A1
公开(公告)日：2009-09-03
申请号：US12453419
申请日：2009-05-11
申请人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
发明人： Ju-Wan Lim , Hyun-Seok Jang , Byung-Hong Chung , Ki-Hyun Hwang , Sang-Ryol Yang
IPC分类号： H01L21/28
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L29/78 , H01L29/7851 , H01L29/792
摘要： A non-volatile memory device prevents charge spreading. The non-volatile memory device includes an isolation trench in a semiconductor substrate, an isolation layer partially filling the isolation trench between first and second fins defined by the isolation trench, a control gate electrode crossing the first and second fins, a first charge trap pattern between the first fin and the control gate electrode, and a second charge trap pattern between the second fin and the control gate electrode.
摘要翻译：非易失性存储器件防止电荷扩展。非易失性存储器件包括半导体衬底中的隔离沟槽，隔离层部分地填充由隔离沟槽限定的第一和第二鳍片之间的隔离沟槽，跨越第一鳍片和第二鳍片的控制栅极电极，第一电荷陷阱图案在第一鳍片和控制栅电极之间，以及第二鳍片和控制栅电极之间的第二电荷陷阱图案。

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