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1. 发明授权

US07772069B2 Methods of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US07772069B2
公开(公告)日：2010-08-10
申请号：US12074992
申请日：2008-03-07
申请人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
发明人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11524 , H01L27/11568
摘要： A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.
摘要翻译：提供一种形成半导体器件的方法。多个第一引导图案形成在基板上。掩模层在基底上共形地形成。第二引导图案形成在第一引导图案的相应侧上的空白区域中。掩模层被平坦化，并且去除第一和第二引导图案。通过各向异性蚀刻工艺蚀刻掩模层。

2. 发明申请

US20080227258A1 Methods of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20080227258A1
公开(公告)日：2008-09-18
申请号：US12074992
申请日：2008-03-07
申请人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
发明人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L27/11521 , H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11524 , H01L27/11568
摘要： Methods of forming a semiconductor device include forming a mask layer on a semiconductor substrate. The mask layer has vertically and horizontally extending portions. The vertically extending portions have a thickness selected to provide a desired line width to an underlying structure to be formed using the mask layer and a height greater than a height of the horizontally extending portions. The underlying structure is formed using the mask layer.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成掩模层。掩模层具有垂直和水平延伸的部分。垂直延伸部分具有选择的厚度，以使要使用掩模层形成的下层结构和高于水平延伸部分的高度的高度提供期望的线宽。使用掩模层形成底层结构。

3. 发明授权

US09117654B2 Methods of forming fine patterns in integrated circuit devices 有权
标题翻译：在集成电路器件中形成精细图案的方法
公开(公告)号：US09117654B2
公开(公告)日：2015-08-25
申请号：US13470773
申请日：2012-05-14
申请人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
发明人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
IPC分类号： H01L21/467 , H01L27/02 , H01L21/033 , H01L21/308 , H01L21/3213 , H01L21/762 , H01L23/544 , H01L27/115 , H01L27/105
CPC分类号： H01L27/0207 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L23/544 , H01L27/1052 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.
摘要翻译：制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。间隔件形成在第一和第二掩模结构的相对侧壁上。第一掩模结构被选择性地从第一区域中的间隔物之间移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案在第二区域中。

4. 发明授权

US08057692B2 Methods of forming fine patterns in the fabrication of semiconductor devices 有权
标题翻译：在半导体器件的制造中形成精细图案的方法
公开(公告)号：US08057692B2
公开(公告)日：2011-11-15
申请号：US12290420
申请日：2008-10-30
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

5. 发明申请

US20140167290A1 METHODS OF FORMING FINE PATTERNS IN THE FABRICATION OF SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件制造中形成精细图案的方法
公开(公告)号：US20140167290A1
公开(公告)日：2014-06-19
申请号：US14186617
申请日：2014-02-21
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： H01L23/528
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

6. 发明授权

US08686563B2 Methods of forming fine patterns in the fabrication of semiconductor devices 有权
标题翻译：在半导体器件的制造中形成精细图案的方法
公开(公告)号：US08686563B2
公开(公告)日：2014-04-01
申请号：US12639542
申请日：2009-12-16
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

7. 发明申请

US20100096719A1 METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES 有权
标题翻译：在集成电路设备中形成精细图案的方法
公开(公告)号：US20100096719A1
公开(公告)日：2010-04-22
申请号：US12418023
申请日：2009-04-03
申请人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
发明人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
IPC分类号： H01L29/06 , H01L21/762 , H01L23/544
CPC分类号： H01L27/0207 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L23/544 , H01L27/1052 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.
摘要翻译：制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。间隔件形成在第一和第二掩模结构的相对侧壁上。使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征。

8. 发明授权

US08216947B2 Methods of forming fine patterns in integrated circuit devices 有权
标题翻译：在集成电路器件中形成精细图案的方法
公开(公告)号：US08216947B2
公开(公告)日：2012-07-10
申请号：US12418023
申请日：2009-04-03
申请人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
发明人： Young-Ho Lee , Jae-Kwan Park , Jae-Hwang Sim , Sang-Yong Park
IPC分类号： H01L21/336 , H01L21/302 , H01L21/4763
CPC分类号： H01L27/0207 , H01L21/0332 , H01L21/0337 , H01L21/3081 , H01L21/3086 , H01L21/32139 , H01L21/76229 , H01L23/544 , H01L27/1052 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature.
摘要翻译：制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。各向同性蚀刻第一和第二掩模结构的蚀刻掩模图案以从第一掩模结构去除蚀刻掩模图案，同时将蚀刻掩模图案的至少一部分保持在第二掩模结构上。间隔件形成在第一和第二掩模结构的相对侧壁上。使用第二掩模结构上的蚀刻掩模图案的部分作为掩模，第一掩模结构从第一区域中的间隔物之间选择性地移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物以及第二掩模图案，其包括在第二区域中具有第二掩模结构的相对的侧壁间隔物。可以使用第一掩模图案作为掩模来对特征层进行图案化，以在第一区域上限定第一特征，并且使用第二掩模图案作为掩模来限定具有比第一特征宽的宽度的第二区域上的第二特征。

9. 发明申请

US20100090349A1 METHODS OF FORMING FINE PATTERNS IN THE FABRICATION OF SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件制造中形成精细图案的方法
公开(公告)号：US20100090349A1
公开(公告)日：2010-04-15
申请号：US12639542
申请日：2009-12-16
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： H01L23/48
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

10. 发明申请

US20090311861A1 Methods of forming fine patterns in the fabrication of semiconductor devices 有权
标题翻译：在半导体器件的制造中形成精细图案的方法
公开(公告)号：US20090311861A1
公开(公告)日：2009-12-17
申请号：US12290420
申请日：2008-10-30
申请人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
发明人： Sang-Yong Park , Jae-Hwang Sim , Young-Ho Lee , Kyung-Lyul Moon , Jae-Kwan Park
IPC分类号： H01L21/302
CPC分类号： H01L23/528 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76838 , H01L21/823456 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.
摘要翻译：在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是位于。模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。间隔层设置在第一区域和第二区域中的模具掩模图案上。执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征。

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