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1. 发明授权

US07772069B2 Methods of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US07772069B2
公开(公告)日：2010-08-10
申请号：US12074992
申请日：2008-03-07
申请人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
发明人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11524 , H01L27/11568
摘要： A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.
摘要翻译：提供一种形成半导体器件的方法。多个第一引导图案形成在基板上。掩模层在基底上共形地形成。第二引导图案形成在第一引导图案的相应侧上的空白区域中。掩模层被平坦化，并且去除第一和第二引导图案。通过各向异性蚀刻工艺蚀刻掩模层。

2. 发明申请

US20080227258A1 Methods of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20080227258A1
公开(公告)日：2008-09-18
申请号：US12074992
申请日：2008-03-07
申请人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
发明人： Sang-Yong Park , Sung-Hyun Kwon , Jae-Hwang Sim , Keon-Soo Kim , Jae-Kwan Park
IPC分类号： H01L21/336 , H01L21/31
CPC分类号： H01L27/11521 , H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11524 , H01L27/11568
摘要： Methods of forming a semiconductor device include forming a mask layer on a semiconductor substrate. The mask layer has vertically and horizontally extending portions. The vertically extending portions have a thickness selected to provide a desired line width to an underlying structure to be formed using the mask layer and a height greater than a height of the horizontally extending portions. The underlying structure is formed using the mask layer.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成掩模层。掩模层具有垂直和水平延伸的部分。垂直延伸部分具有选择的厚度，以使要使用掩模层形成的下层结构和高于水平延伸部分的高度的高度提供期望的线宽。使用掩模层形成底层结构。

3. 发明授权

US08592273B2 Method of manufacturing nonvolatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08592273B2
公开(公告)日：2013-11-26
申请号：US13230228
申请日：2011-09-12
申请人： Jae-Hwang Sim , Keon-Soo Kim , Kyung-Hoon Min , Min-Sung Song , Yeon-Wook Jung
发明人： Jae-Hwang Sim , Keon-Soo Kim , Kyung-Hoon Min , Min-Sung Song , Yeon-Wook Jung
IPC分类号： H01L21/336
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.
摘要翻译：在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。在基板的有源区上形成第一电介质图案。导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

4. 发明授权

US08183152B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08183152B2
公开(公告)日：2012-05-22
申请号：US12904363
申请日：2010-10-14
申请人： Jae-Hwang Sim , Yoon-Moon Park , Keon-Soo Kim , Min-Sung Song , Young-Ho Lee
发明人： Jae-Hwang Sim , Yoon-Moon Park , Keon-Soo Kim , Min-Sung Song , Young-Ho Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/32139 , H01L21/0337 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , Y10S438/947
摘要： A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask.
摘要翻译：制造半导体器件的方法有助于形成具有不同宽度的特征的导电图案。在基板上形成导电层，在导电层上形成掩模层。在掩模层上形成第一间隔开的图案，并且在掩模层上的第一图案旁边形成包括第一和第二平行部分的第二图案。第一辅助掩模分别形成在第一图案的端部上，并且第二辅助掩模形成在第二图案上，跨越第二图案的第一和第二部分。然后蚀刻掩模层以在第一图案下方形成第一掩模图案，并在第二图案下方形成第二掩模图案。去除第一和第二图案以及第一和第二辅助掩模。然后使用第一和第二掩模图案作为蚀刻掩模蚀刻导电层。

5. 发明申请

US20120132976A1 SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME 有权
标题翻译：具有双重TRENCH的半导体器件，其制造方法以及具有其的电子系统
公开(公告)号：US20120132976A1
公开(公告)日：2012-05-31
申请号：US13368556
申请日：2012-02-08
申请人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
发明人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
IPC分类号： H01L29/788 , H01L29/06
CPC分类号： H01L21/76229
摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.
摘要翻译：提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。芯绝缘材料层具有比填充绝缘材料层更大的流动性。

6. 发明授权

US08187935B2 Method of forming active region structure 有权
标题翻译：形成有源区结构的方法
公开(公告)号：US08187935B2
公开(公告)日：2012-05-29
申请号：US12795025
申请日：2010-06-07
申请人： Young-Ho Lee , Keon-Soo Kim , Jae-Hwang Sim , Jin-Hyun Shin , Kyung-Hoon Min
发明人： Young-Ho Lee , Keon-Soo Kim , Jae-Hwang Sim , Jin-Hyun Shin , Kyung-Hoon Min
IPC分类号： H01L21/8247
CPC分类号： H01L21/76229 , H01L21/823481 , H01L27/1052
摘要： A method of forming an active region structure includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region, forming upper cell mask patterns having a line shape in the cell array region, forming first and second peripheral mask patterns in the peripheral circuit region, the first and second peripheral mask patterns being stacked in sequence and covering the peripheral circuit region, and upper surfaces of the upper cell mask patterns forming a step difference with an upper surface of the second peripheral mask pattern, forming spacers on sidewalls of the upper cell mask patterns to expose lower portions of the upper cell mask patterns and the second peripheral mask pattern, and removing the lower portions of the upper cell mask patterns using the spacers and the first and second peripheral mask patterns as an etch mask.
摘要翻译：形成有源区域结构的方法包括制备具有单元阵列区域和外围电路区域的半导体衬底，在单元阵列区域中形成具有线状的上层单元掩模图案，在外围电路中形成第一和第二外围掩模图案区域，第一外围掩模图案和第二外围掩模图案依次堆叠并覆盖外围电路区域，并且上部单元掩模图案的上表面与第二外围掩模图案的上表面形成阶梯差，在第二外围掩模图案的侧壁上形成间隔物上部单元掩模图案以暴露上部单元掩模图案和第二外围掩模图案的下部，并且使用间隔件和第一外围掩模图案和第二外围掩模图案作为蚀刻掩模去除上部单元掩模图案的下部。

7. 发明授权

US08519484B2 Semiconductor devices having dual trench, methods of fabricating the same, and electronic system having the same 有权
标题翻译：具有双沟槽的半导体器件及其制造方法以及具有该半导体器件的电子系统
公开(公告)号：US08519484B2
公开(公告)日：2013-08-27
申请号：US13368556
申请日：2012-02-08
申请人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
发明人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
IPC分类号： H01L21/70
CPC分类号： H01L21/76229
摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.
摘要翻译：提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。芯绝缘材料层具有比填充绝缘材料层更大的流动性。

8. 发明申请

US20120064710A1 METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20120064710A1
公开(公告)日：2012-03-15
申请号：US13230228
申请日：2011-09-12
申请人： Jae-Hwang Sim , Keon-Soo Kim , Kyung-Hoon Min , Min-Sung Song , Yeon-Wook Jung
发明人： Jae-Hwang Sim , Keon-Soo Kim , Kyung-Hoon Min , Min-Sung Song , Yeon-Wook Jung
IPC分类号： H01L21/28
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.
摘要翻译：在非易失性存储器件及其制造方法中，器件隔离图案和有源区域在衬底上沿第一方向延伸。在基板的有源区上形成第一电介质图案。导电堆叠结构布置在第一电介质图案上，并且在一对相邻的导电堆叠结构之间形成凹部。保护层形成在堆叠结构的侧壁上，以保护堆叠结构的侧壁不沿着第一方向过度蚀刻。保护层包括具有氧化物并设置在浮栅电极的侧壁上的防蚀层和控制栅极线的侧壁以及覆盖导电堆叠结构侧壁的间隔层。

9. 发明授权

US08129238B2 Semiconductor devices having dual trench, methods of fabricating the same, and electronic system having the same 有权
标题翻译：具有双沟槽的半导体器件及其制造方法以及具有该半导体器件的电子系统
公开(公告)号：US08129238B2
公开(公告)日：2012-03-06
申请号：US12951490
申请日：2010-11-22
申请人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
发明人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
IPC分类号： H01L21/8242
CPC分类号： H01L21/76229
摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.
摘要翻译：提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。芯绝缘材料层具有比填充绝缘材料层更大的流动性。

10. 发明申请

US20110165757A1 SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME 有权
标题翻译：具有双重TRENCH的半导体器件，其制造方法以及具有其的电子系统
公开(公告)号：US20110165757A1
公开(公告)日：2011-07-07
申请号：US12951490
申请日：2010-11-22
申请人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
发明人： Dong-Won Kim , Jae-Hwang Sim , Keon-Soo Kim , Young-Ho Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/76229
摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.
摘要翻译：提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。芯绝缘材料层具有比填充绝缘材料层更大的流动性。

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