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1. 发明授权

US08140756B2 Information handling system with immediate scheduling of load operations and fine-grained access to cache memory 有权
标题翻译：信息处理系统，可立即调度加载操作，并对缓存进行细粒度访问
公开(公告)号：US08140756B2
公开(公告)日：2012-03-20
申请号：US12424332
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0822
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。控制逻辑确定每个加载操作或存储操作的大小要求。当高速缓冲存储器系统执行存储操作或加载操作时，存储器系统访问它需要执行操作的高速缓存行的部分，而不是访问整个高速缓存行。

2. 发明授权

US08195880B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow 有权
标题翻译：信息处理系统，具有双重缓存中的负载操作的即时调度，具有双重调度到写入/读取数据流
公开(公告)号：US08195880B2
公开(公告)日：2012-06-05
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

3. 发明授权

US08140765B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow 有权
标题翻译：信息处理系统，可以在双行缓存中立即调度负载操作，并单次调度到写入/读取数据流
公开(公告)号：US08140765B2
公开(公告)日：2012-03-20
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/28
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

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