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1. 发明申请

US20130332781A1 RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS 有权
标题翻译： INPUT / OUPUT ERROR-CONTAINENT事件后恢复
公开(公告)号：US20130332781A1
公开(公告)日：2013-12-12
申请号：US13997870
申请日：2012-06-06
申请人： Sarathy Jayakumar , Mohan J. Kumar , Jose A. Vargas
发明人： Sarathy Jayakumar , Mohan J. Kumar , Jose A. Vargas
IPC分类号： G06F11/07
CPC分类号： G06F11/0751 , G06F11/0712 , G06F11/0745 , G06F11/0793
摘要： Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.
摘要翻译：本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器输入/输出错误容纳事件。在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

2. 发明授权

US09411667B2 Recovery after input/ouput error-containment events 有权
标题翻译：输入/输出错误控制事件后恢复
公开(公告)号：US09411667B2
公开(公告)日：2016-08-09
申请号：US13997870
申请日：2012-06-06
申请人： Sarathy Jayakumar , Mohan J. Kumar , Jose A. Vargas
发明人： Sarathy Jayakumar , Mohan J. Kumar , Jose A. Vargas
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0751 , G06F11/0712 , G06F11/0745 , G06F11/0793
摘要： Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.
摘要翻译：本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器输入/输出错误容纳事件。在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

3. 发明申请

US20210096848A1 SECURE AND EFFICIENT MICROCODE(UCODE) HOT-UPGRADE FOR BARE METAL CLOUD 有权
公开(公告)号：US20210096848A1
公开(公告)日：2021-04-01
申请号：US17120072
申请日：2020-12-11
申请人： Sarathy Jayakumar , Chuan Song , Mohan J. Kumar
发明人： Sarathy Jayakumar , Chuan Song , Mohan J. Kumar
IPC分类号： G06F8/656 , G06F9/48 , G06F9/4401 , G06F9/455 , G06F12/1027
摘要： A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. Under the uCode hot-upgrade method, a uCode path is received at an out-of-band controller (e.g., baseboard management controller (BMC)) and buffered in a memory buffer in the out-of-band controller. The out-of-band controller exposes the memory buffer as a Memory-Mapped Input-Output (MMIO) range to a host CPU. A uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for live-patch without touching the tenant operating system environment.

4. 发明申请

US20200285461A1 MICROCODE(UCODE) HOT-UPGRADE METHOD FOR BARE METAL CLOUD DEPLOYMENT 审中-公开
公开(公告)号：US20200285461A1
公开(公告)日：2020-09-10
申请号：US16841410
申请日：2020-04-06
申请人： Mohan J. Kumar , Sarathy Jayakumar , Chuan Song , Ruixia Li , Xiaojin Yuan , Haiyue Wang , Chong Han
发明人： Mohan J. Kumar , Sarathy Jayakumar , Chuan Song , Ruixia Li , Xiaojin Yuan , Haiyue Wang , Chong Han
IPC分类号： G06F8/656 , G06F8/654 , G06F9/4401 , G06F9/445
摘要： A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.

5. 发明申请

US20150089287A1 EVENT-TRIGGERED STORAGE OF DATA TO NON-VOLATILE MEMORY 审中-公开
标题翻译：事件触发数据存储到非易失性存储器
公开(公告)号：US20150089287A1
公开(公告)日：2015-03-26
申请号：US14127548
申请日：2013-09-23
申请人： Sarathy Jayakumar , Mohan J. Kumar , Krishnakanth V. Sistla
发明人： Sarathy Jayakumar , Mohan J. Kumar , Krishnakanth V. Sistla
IPC分类号： G06F11/07 , G06F13/24 , G06F11/30 , G06F12/08 , G06F11/16 , G06F1/30
CPC分类号： G06F11/079 , G06F1/30 , G06F11/14 , G06F11/1441 , G06F11/165 , G06F11/2015 , G06F11/3031 , G06F11/3072 , G06F12/0802 , G06F12/0804 , G06F13/24 , G06F2201/86
摘要： An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system.
摘要翻译：事件管理资源监视处理器环境。响应于在处理器环境中检测到触发事件的发生，事件管理资源启动处理器高速缓存数据从处理器环境中的易失性存储器传送到非易失性存储器。可以将事件管理资源配置为产生与缓存数据传送相关联的状态信息到相应的非易失性存储器资源。事件管理资源将状态信息存储在非易失性存储资源中，供以后检索。因此，与导致传送的事件相关联的状态信息可用于在随后的相应计算机系统的加电或重新启动时进行分析。

6. 发明申请

US20090172372A1 METHODS AND APPARATUS FOR GENERATING SYSTEM MANAGEMENT INTERRUPTS 有权
标题翻译：用于生成系统管理中断的方法和装置
公开(公告)号：US20090172372A1
公开(公告)日：2009-07-02
申请号：US11967299
申请日：2007-12-31
申请人： Mohan J. Kumar , Sarathy Jayakumar , Sham Datta
发明人： Mohan J. Kumar , Sarathy Jayakumar , Sham Datta
IPC分类号： G06F9/26
CPC分类号： G06F9/4812
摘要： A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.
摘要翻译：一种方法包括确定多个存储器地址，每个存储器地址彼此不同。该方法还包括产生多个系统管理中断处理器中断，每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器，并且每个系统管理中断处理器中断包括多个存储器地址之一。该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。还公开了一种相关的机器可读介质。

7. 发明申请

US20160378697A1 PROVIDING DEDICATED RESOURCES FOR A SYSTEM MANAGEMENT MODE OF A PROCESSOR 审中-公开
标题翻译：为处理器的系统管理模式提供专用资源
公开(公告)号：US20160378697A1
公开(公告)日：2016-12-29
申请号：US14749893
申请日：2015-06-25
申请人： Sarathy Jayakumar , Ashok Raj , John G. Holm , Narayan Ranganathan , Mohan J. Kumar , Sergiu D. Ghetie
发明人： Sarathy Jayakumar , Ashok Raj , John G. Holm , Narayan Ranganathan , Mohan J. Kumar , Sergiu D. Ghetie
IPC分类号： G06F13/24 , G06F9/44 , G06F1/32
CPC分类号： G06F13/24 , G06F1/3228 , G06F1/3287 , G06F9/4405 , G06F9/4406 , Y02D10/171
摘要： In one embodiment, a processor includes a plurality of cores including a first core to be reserved for execution in a protected domain, the first core to be hidden from an operating system. The processor may further include a filter coupled to the plurality of cores, where the filter includes a plurality of fields each associated with one of the plurality of cores to indicate whether an interrupt of the protected domain is to be directed to the corresponding core. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括多个核心，其包括待保留用于在受保护的域中执行的第一核心，第一核心从操作系统隐藏。处理器还可以包括耦合到多个核的滤波器，其中滤波器包括多个场，每个场与多个核中的一个相关联，以指示受保护域的中断是否被引导到对应的核。描述和要求保护其他实施例。

8. 发明申请

US20150161037A1 FAST CACHE FLUSH 有权
标题翻译：快速缓存
公开(公告)号：US20150161037A1
公开(公告)日：2015-06-11
申请号：US14100721
申请日：2013-12-09
申请人： Sarathy Jayakumar , Mohan J. Kumar , Eswaramoorthi Nallusamy
发明人： Sarathy Jayakumar , Mohan J. Kumar , Eswaramoorthi Nallusamy
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F12/0868 , G06F12/0891 , G06F2212/1032 , G06F2212/7203
摘要： Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in a volatile memory, determine whether the first data element is to be stored in a nonvolatile memory, and in response to a determination that the first data element is to be stored in a nonvolatile memory, to forward the first transaction to the memory controller coupled to the nonvolatile memory. Other examples are also disclosed and claimed.
摘要翻译：描述了管理存储器操作的装置，系统和方法。在一个示例中，控制器包括接收第一事务以操作易失性存储器中的第一数据元素的逻辑，确定第一数据元素是否要存储在非易失性存储器中，并且响应于确定第一数据元件将被存储在非易失性存储器中，以将第一事务转发到耦合到非易失性存储器的存储器控制器。还公开并要求保护其他实例。

9. 发明申请

US20140281092A1 SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS 有权
标题翻译：多核处理器的系统管理中断处理
公开(公告)号：US20140281092A1
公开(公告)日：2014-09-18
申请号：US13799327
申请日：2013-03-13
申请人： Sarathy Jayakumar , Mohan J. Kumar , Michael D. Kinney
发明人： Sarathy Jayakumar , Mohan J. Kumar , Michael D. Kinney
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F11/0772
摘要： Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.
摘要翻译：用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。其他处理器核心执行从属SMI处理程序。主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。描述和要求保护其他实施例。

10. 发明申请

US20150378841A1 Techniques to Communicate with a Controller for a Non-Volatile Dual In-Line Memory Module 有权
标题翻译：与非易失性双列直插式存储器模块的控制器进行通信的技术
公开(公告)号：US20150378841A1
公开(公告)日：2015-12-31
申请号：US14319361
申请日：2014-06-30
申请人： Sarathy Jayakumar , Mohan J. Kumar , Adam J. Brooks , George Vergis
发明人： Sarathy Jayakumar , Mohan J. Kumar , Adam J. Brooks , George Vergis
IPC分类号： G06F11/14 , G06F3/06 , G11C14/00 , G06F9/44
CPC分类号： G06F9/4401 , G06F11/1441 , G06F11/2015
摘要： Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map.
摘要翻译：示例可以包括通过系统管理总线（SMBus）接口与用于非易失性双列直插存储器模块的控制器进行通信。在一些示例中，通过SMBus接口可访问的寄存器中保持的位的选择性断言可以实现与控制器的通信。选择性断言可以基于寄存器映射。

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