专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090307557A1 Packet Re-transmission Controller for Block Acknowledgement in a Communications System 有权
公开(公告)号：US20090307557A1
公开(公告)日：2009-12-10
申请号：US12134213
申请日：2008-06-06
申请人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
发明人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
IPC分类号： H04L1/18 , G06F11/00
CPC分类号： H04L1/1874
摘要： A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with said pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.

2. 发明授权

US08151155B2 Packet Re-transmission controller for block acknowledgement in a communications system 有权
标题翻译：分组重传控制器，用于通信系统中的块确认
公开(公告)号：US08151155B2
公开(公告)日：2012-04-03
申请号：US12134213
申请日：2008-06-06
申请人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
发明人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
IPC分类号： H04L1/18 , G08C25/02
CPC分类号： H04L1/1874
摘要： A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with the pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.
摘要翻译：用于无线通信系统的再发送处理器包括指针存储器，其包含与主机存储器中的特定分组数据相关联的指针。重发送处理器将与要应用于指示符的指针相关联的数据指向媒体访问控制器，该媒体访问控制器可选地包含加密功能，其输出耦合到块缓冲器和输出接口。在接收到发送请求时，读取与指针相关联的主存储器位置，并且指向媒体访问控制器的数据，其添加报头，CRC，并且可选地加密数据，然后将其放入块缓冲器中，并且输出接口。在将分组数据提供给MAC时，相关联的指针被初始化为FREE或UNUSED值，并且当从接收站接收到伴随分组标识符的分组的确认时，去除与分组标识符相关联的分组从块缓冲区。

3. 发明授权

US07957273B2 Packet re-transmission controller for block acknowledgement in a communications system 有权
标题翻译：用于通信系统中的块确认的分组重传控制器
公开(公告)号：US07957273B2
公开(公告)日：2011-06-07
申请号：US12134204
申请日：2008-06-06
申请人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
发明人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
IPC分类号： H04J3/14
CPC分类号： H04L1/1685 , H04L1/187
摘要： A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with said pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.
摘要翻译：用于无线通信系统的再发送处理器包括指针存储器，其包含与主机存储器中的特定分组数据相关联的指针。重新发送处理器将与要应用于所述指针相关联的数据指向要被应用于媒体访问控制器的数据，所述媒体访问控制器可选地包含加密功能，其输出耦合到块缓冲器和输出接口。在接收到发送请求时，读取与指针相关联的主存储器位置，并且指向媒体访问控制器的数据，其添加报头，CRC，并且可选地加密数据，然后将其放入块缓冲器中，并且输出接口。在将分组数据提供给MAC时，相关联的指针被初始化为FREE或UNUSED值，并且当从接收站接收到伴随分组标识符的分组的确认时，去除与分组标识符相关联的分组从块缓冲区。

4. 发明申请

US20090303998A1 Packet Re-transmission Controller for Block Acknowledgement in a Communications System 有权
标题翻译：分组重传控制器，用于通信系统中的块确认
公开(公告)号：US20090303998A1
公开(公告)日：2009-12-10
申请号：US12134204
申请日：2008-06-06
申请人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
发明人： Satyanarayana Rao , Venkata Rao Gunturu , Narasimhan Venkatesh
IPC分类号： H04L12/56
CPC分类号： H04L1/1685 , H04L1/187
摘要： A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with said pointers to be applied to a media access controller, which optionally contains an encryption function, the output of which is coupled to a block buffer and to an output interface. Upon receipt of a transmission request, the host memory locations associated with the pointers are read and the data directed to the media access controller, which adds a header, a CRC, and optionally encrypts the data, thereafter placing it in the block buffer and the output interface. Upon provision of the packet data to the MAC, the associated pointer is initialized to a FREE or UNUSED value, and upon receipt of an acknowledgement of the packet accompanied by a packet identifier from a receiving station, the packet associated with the packet identifier is removed from the block buffer.
摘要翻译：用于无线通信系统的再发送处理器包括指针存储器，其包含与主机存储器中的特定分组数据相关联的指针。重新发送处理器将与要应用于所述指针相关联的数据指向要被应用于媒体访问控制器的数据，所述媒体访问控制器可选地包含加密功能，其输出耦合到块缓冲器和输出接口。在接收到发送请求时，读取与指针相关联的主存储器位置，并且指向媒体访问控制器的数据，其添加报头，CRC，并且可选地加密数据，然后将其放入块缓冲器中，并且输出接口。在将分组数据提供给MAC时，相关联的指针被初始化为FREE或UNUSED值，并且当从接收站接收到伴随分组标识符的分组的确认时，去除与分组标识符相关联的分组从块缓冲区。

5. 发明授权

US07298799B1 All-tap fractionally spaced, serial rake combiner apparatus and method 有权
$All-tap fractionally spaced, serial rake combiner apparatus and method$
标题翻译：全抽头间距，串联耙组合器装置及方法
公开(公告)号：US07298799B1
公开(公告)日：2007-11-20
申请号：US10795817
申请日：2004-03-08
申请人： Narasimhan Venkatesh , Sankabathula Dharani Naga Sailaja , Murali Partha Sarathy
发明人： Narasimhan Venkatesh , Sankabathula Dharani Naga Sailaja , Murali Partha Sarathy
IPC分类号： H04L27/06
CPC分类号： H04B1/7093 , H04B1/7077 , H04B1/712
摘要： A decision processor for 802.11b codewords for 1 Mb and 2 Mb data rates includes a sliding correlator for the acquisition of correlation peaks. During a training interval, these correlation peaks are summed into a channel profile memory. The correlation peaks corresponding to a codeword are added into the channel profile memory, and correlation peaks corresponding to the inverse of this codeword are inverted and added into the channel profile memory during the training interval. After the training interval, a decision interval follows whereby correlation peaks are multiplied by the complex conjugate of the contents of the channel profile memory. The multiplication results are accumulated over a codeword window interval to produce a decision output.
摘要翻译：用于1Mb和2Mb数据速率的用于802.11b码字的决策处理器包括用于获取相关峰值的滑动相关器。在训练间隔期间，将这些相关峰值相加到通道轮廓存储器中。对应于码字的相关峰值被加入到信道简档存储器中，并且与该码字的逆相对应的相关峰值在训练间隔期间被反转并添加到信道简档存储器中。在训练间隔之后，确定间隔，由此将相关峰乘以信道简档存储器的内容的复共轭。乘法结果在码字窗口间隔上累加以产生决策输出。

6. 发明授权

US08879527B1 Access point processor for a wireless local area network utilizing multiple sub-channels 有权
标题翻译：使用多个子信道的无线局域网的接入点处理器
公开(公告)号：US08879527B1
公开(公告)日：2014-11-04
申请号：US13278436
申请日：2011-10-21
申请人： Narasimhan Venkatesh
发明人： Narasimhan Venkatesh
IPC分类号： H04W4/00
CPC分类号： H04W4/00 , H04W28/16 , H04W72/00 , H04W84/12
摘要： A channel access processor for an access point operates in a frequency spectrum which is divided into master channels, each master channel further having a plurality of sub-channels, each sub-channel capable of supporting wireless LAN communications independently from any other said sub-channel of the master channel. Each master channel is thereby associated with a plurality of sub-channels, and the sub-channels each have an associated bandpass filter and mixer frequency specific to that sub-channel, thereby allowing a plurality of independent wireless communications sessions to simultaneously take place over the multiple sub-channels of the master channel of the access point.
摘要翻译：用于接入点的信道接入处理器在被分成主信道的频谱中操作，每个主信道还具有多个子信道，每个子信道能够独立于任何其它所述子信道支持无线LAN通信的主频道。因此，每个主信道与多个子信道相关联，并且子信道各自具有相关联的带通滤波器和该子信道特有的混频器频率，从而允许多个独立的无线通信会话同时发生在接入点主信道的多个子信道。

7. 发明授权

US07386074B1 Digital automatic gain control method and apparatus 有权
标题翻译：数字自动增益控制方法及装置
公开(公告)号：US07386074B1
公开(公告)日：2008-06-10
申请号：US10680620
申请日：2003-10-06
申请人： Narasimhan Venkatesh , Satya Rao , Dharani Naga Sailaja Sankabathula , Partha Sarathy Murali
发明人： Narasimhan Venkatesh , Satya Rao , Dharani Naga Sailaja Sankabathula , Partha Sarathy Murali
IPC分类号： H04L27/08
CPC分类号： H03G3/3068 , H03G3/3078
摘要： An RF receiver which produces quadrature digitized outputs and has a gain control is coupled to a digital gain controller which converts the quadrature digitized outputs into an rms voltage, and iterates over a finite number of steps to quickly control the gain to a level sufficient to achieve subsequent digital signal processing without limitations caused by insufficient dynamic range or nonlinear saturation effects caused by insufficient signal or excessive signal at the A/D input, respectively.
摘要翻译：产生正交数字化输出并具有增益控制的RF接收器耦合到数字增益控制器，该数字增益控制器将正交数字化输出转换成有效值电压，并且迭代有限数量的步骤以将增益快速控制到足以实现的水平分别由于信号不足或A / D输入过大信号引起的动态范围不足或非线性饱和效应引起的后续数字信号处理。

8. 发明授权

US07296100B1 Packet buffer management apparatus and method 有权
标题翻译：包缓冲管理装置和方法
公开(公告)号：US07296100B1
公开(公告)日：2007-11-13
申请号：US10680660
申请日：2003-10-06
申请人： Narasimhan Venkatesh , Satya Rao
发明人： Narasimhan Venkatesh , Satya Rao
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/128
摘要： A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system removes packets including a packet header and packet data from a packet buffer. The packet buffer is arranged into a plurality of packet buffer memory slots, each slot comprising a descriptor status array location including an availability bit set to “used” or “free”, and a packet buffer memory location comprising a descriptor memory slot and a data segment memory slot. The descriptor memory slot includes header information for each packet, and the data segment memory slot includes packet data. The memory controller operates on one or more queues of data, and data is placed into a particular queue in packet memory determined by priority information derived from incoming packet header or packet data. Data is removed from packet memory based on which queue the data may be found in. The queues are based on a priority system, where one queue receives priority over another queue for data reception and transmission.
摘要翻译：用于无线通信系统的存储器控制器包括分组缓冲器写入系统和分组缓冲器读取系统。分组缓冲器写入系统将包括分组报头和分组数据的分组放入分组缓冲器中。分组缓冲器读取系统从分组缓冲器中去除包括分组报头和分组数据的分组。分组缓冲器被布置成多个分组缓冲存储器时隙，每个时隙包括描述符状态阵列位置，包括设置为“已使用”或“空闲”的可用性位，以及包含描述符存储器时隙和数据的分组缓冲存储器位置段内存插槽。描述符存储器插槽包括每个分组的标题信息，并且数据段存储器时隙包括分组数据。存储器控制器在一个或多个数据队列上操作，并且数据被放置在由从输入分组报头或分组数据导出的优先级信息确定的分组存储器中的特定队列中。基于哪个队列可以找到数据，从数据包存储器中删除数据。队列基于优先级系统，其中一个队列通过另一个队列接收优先级以进行数据接收和传输。

9. 发明授权

US08161205B1 Packet buffer management apparatus and method 有权
标题翻译：包缓冲管理装置和方法
公开(公告)号：US08161205B1
公开(公告)日：2012-04-17
申请号：US11803809
申请日：2007-05-16
申请人： Narasimhan Venkatesh , Satya Rao
发明人： Narasimhan Venkatesh , Satya Rao
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/128
摘要： A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one non-zero element in a row, such that the product of R and Q produces matrix H. A second variable transformation part column-swaps matrix H to form H′, thereafter generating Q′ and R′ subject to the same constraints as was described for Q and R. Transformed variables Z and Z′ are formed by multiplying Y by QH and Q′H, respectively. A reduced complexity maximum likelihood decoder has a first part which accepts Z and R and forms a first metric table having entries of all possible x2 accompanied by estimates of x1 derived from x2 and Z, and also including a distance metric. The reduced complexity maximum likelihood decoder has a second part which accepts Z′ and R′ and forms a second metric table having entries of all possible x1 accompanied by estimates of x2 derived from x1 and Z′, and also including a distance metric. A hard decision is made by finding the minimum distance metric of the combined entries of the first and second table. Soft values are also computed using this table.
摘要翻译：减少的复杂度最大似然解码器接收伴随有信道估计矩阵H的接收符号Y的流。可变变换部分包括通过计算具有至少一个非零的矩阵R将Y和H转换为Z和R的第一部分使得R和Q的乘积产生矩阵H.第二可变变换部分将矩阵H交替以形成H'，之后产生与描述为Q和Q相同约束的Q'和R' 变换变量Z和Z'分别通过将Y乘以QH和Q'H来形成。降低的复杂度最大似然解码器具有接受Z和R的第一部分，并形成具有所有可能x2的条目的第一度量表，伴随着从x2和Z导出的x1的估计，并且还包括距离度量。降低的复杂度最大似然解码器具有接受Z'和R'的第二部分，并且形成具有所有可能的条目的第二度量表，伴随着从x1和Z'导出的x2的估计，并且还包括距离度量。通过找到第一和第二表的组合条目的最小距离度量来做出硬决定。软值也使用此表计算。

10. 发明申请

US20090199037A1 Wake-up timer with periodic recalibration 审中-公开
标题翻译：唤醒定时器，定时重新校准
公开(公告)号：US20090199037A1
公开(公告)日：2009-08-06
申请号：US12024748
申请日：2008-02-01
申请人： Narasimhan Venkatesh , Subba Reddy Kallam , Alukuru Trikutam Sivaram
发明人： Narasimhan Venkatesh , Subba Reddy Kallam , Alukuru Trikutam Sivaram
IPC分类号： G06F1/06 , G06F1/32
CPC分类号： G06F1/12 , G06F1/3203 , Y02D10/126
摘要： A power saving sleep timer has a first clock and a second clock having greater frequency and temporal stability than the first clock. The second clock has an associated second clock period value which is accumulated once for each said second clock interval during one or more first clock periods, thereby forming a calibrated period value. During an operational interval, the calibrated period value is accumulated once per first clock interval until the accumulated value is equal or greater than a sleep time value, after which a power-up output is asserted.
摘要翻译：省电睡眠定时器具有比第一时钟具有更大的频率和时间稳定性的第一时钟和第二时钟。第二时钟具有关联的第二时钟周期值，其在一个或多个第一时钟周期期间针对每个所述第二时钟间隔被累积一次，从而形成校准的周期值。在操作间隔期间，校准周期值每第一时钟间隔累积一次，直到累加值等于或大于睡眠时间值，之后断言上电输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式