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    • 2. 发明申请
    • Semiconductor device and method for manufacturing the same
    • 半导体装置及其制造方法
    • US20060017116A1
    • 2006-01-26
    • US11186396
    • 2005-07-21
    • Seok-Su Kim
    • Seok-Su Kim
    • H01L29/792
    • H01L21/76802H01L21/28525H01L21/76801H01L21/76837H01L21/823425
    • A method for manufacturing a semiconductor device includes forming a gate insulating layer, a gate and a protective layer on a semiconductor substrate, forming a spacer on lateral sides of the protective layer and the gate, forming one or more junction regions in the semiconductor substrate at sides of the gate, partially filling a gap between adjacent gates by selectively forming a conductive layer on an exposed portion of the semiconductor substrate between the adjacent gates, forming an insulating layer over the semiconductor substrate so as to fill a full height of the gap between the adjacent gates, and forming a contact hole partially exposing the conductive layer by etching the insulating layer.
    • 一种半导体器件的制造方法包括在半导体衬底上形成栅极绝缘层,栅极和保护层,在保护层和栅极的侧面形成间隔物,在半导体衬底中形成一个或多个结区域 通过在相邻栅极之间的半导体衬底的暴露部分上选择性地形成导电层,在相邻栅极之间部分地填充间隙,在半导体衬底上形成绝缘层,以便填充半导体衬底之间的间隙的全高 并且通过蚀刻绝缘层形成部分暴露导电层的接触孔。
    • 4. 发明授权
    • Method for forming an MIM capacitor
    • MIM电容器的形成方法
    • US06818499B2
    • 2004-11-16
    • US10624676
    • 2003-07-23
    • Seok-Su Kim
    • Seok-Su Kim
    • H01L218242
    • H01L28/60H01L21/32136
    • A method for forming a metal-insulator-metal (“MIM”) capacitor is provided. In the method, a first metal film and an dielectric film are sequentially formed on a semiconductor substrate. A trench through which the first metal film is exposed is formed by patterning the dielectric film. A insulation film and a second metal film are sequentially formed on a surface of the trench and the dielectric film. A mask pattern defining a capacitor forming area is provided on the second metal film. The second metal film and the insulation film are etched by using the mask pattern and the dielectric film as an etching barrier and an etching stopper layer, respectively, to form an upper electrode. With the mask pattern removed, a lower electrode is formed by patterning the dielectric film and the first metal film.
    • 提供了形成金属 - 绝缘体 - 金属(“MIM”)电容器的方法。 在该方法中,在半导体基板上依次形成第一金属膜和电介质膜。 通过图案化电介质膜来形成暴露第一金属膜的沟槽。 绝缘膜和第二金属膜依次形成在沟槽和电介质膜的表面上。 在第二金属膜上设置限定电容器形成区域的掩模图案。 通过使用掩模图案和电介质膜分别作为蚀刻阻挡层和蚀刻停止层来分别蚀刻第二金属膜和绝缘膜,以形成上电极。 通过去除掩模图案,通过图案化电介质膜和第一金属膜来形成下电极。
    • 5. 发明授权
    • Circuit driving for liquid crystal display device
    • 液晶显示装置的电路驱动
    • US08436849B2
    • 2013-05-07
    • US12822827
    • 2010-06-24
    • Soo-Ho JangSeok-Su KimTae-Young Jung
    • Soo-Ho JangSeok-Su KimTae-Young Jung
    • G06F3/038
    • G09G3/3677G09G2320/0247
    • The present invention relates to a circuit for driving a liquid crystal display device in which no multi-flicker preventive signal FLK, but only single flicker preventive signal FLK, is used for reducing numbers of pins of a timing controller and a level shifter. The circuit for driving a liquid crystal display device includes a liquid crystal panel having a plurality of pixel regions for displaying an image, a timing controller for generating one flicker preventive signal and a plurality of clock signals and gate control signals to control driving timing of a gate driver, a gate pulse modulation unit for logically operating the one flicker preventive signal and the plurality of clock signals from the timing controller to generate a plurality of flicker preventive signals, and modulating a gate high voltage from the timing controller according to each of the plurality of flicker preventive signals generated thus to generate a plurality of modulated gate on voltages; a level shifter unit for changing the plurality of clock signals from the timing controller according to the plurality of modulated gate on voltages from the gate pulse modulation unit and a gate low voltage from the timing controller to generate a plurality of level shifted and modulated clock signals; and a gate driver for driving gate lines on the liquid crystal panel according to the a plurality of level shifted and modulated clock signals.
    • 本发明涉及一种用于驱动液晶显示装置的电路,其中不使用多闪烁防止信号FLK,而仅使用单个防闪烁信号FLK来减少定时控制器和电平转换器的引脚数。 用于驱动液晶显示装置的电路包括具有用于显示图像的多个像素区域的液晶面板,用于产生一个防闪烁信号的定时控制器,以及多个时钟信号和门控制信号,以控制液晶显示装置的驱动定时 栅极驱动器,门脉冲调制单元,用于逻辑地操作来自定时控制器的一个防闪烁信号和多个时钟信号,以产生多个防闪烁信号,并且根据每个的时序控制器调制栅极高电压 多个防止闪烁信号产生,从而产生多个调制栅极电压; 电平移位器单元,用于根据来自门脉冲调制单元的多个调制栅极导通电压和来自定时控制器的栅极低电压,从定时控制器改变多个时钟信号,以产生多个电平移位和调制时钟信号 ; 以及用于根据多个电平移位和调制时钟信号在液晶面板上驱动栅极线的栅极驱动器。
    • 6. 发明申请
    • CIRCUIT DRIVING FOR LIQUID CRYSTAL DISPLAY DEVICE
    • 液晶显示装置的电路驱动
    • US20110157148A1
    • 2011-06-30
    • US12822827
    • 2010-06-24
    • Soo-Ho JangSeok-Su KimTae-Young Jung
    • Soo-Ho JangSeok-Su KimTae-Young Jung
    • G06F3/038
    • G09G3/3677G09G2320/0247
    • The present invention relates to a circuit for driving a liquid crystal display device in which no multi-flicker preventive signal FLK, but only single flicker preventive signal FLK, is used for reducing numbers of pins of a timing controller and a level shifter. The circuit for driving a liquid crystal display device includes a liquid crystal panel having a plurality of pixel regions for displaying an image, a timing controller for generating one flicker preventive signal and a plurality of clock signals and gate control signals to control driving timing of a gate driver, a gate pulse modulation unit for logically operating the one flicker preventive signal and the plurality of clock signals from the timing controller to generate a plurality of flicker preventive signals, and modulating a gate high voltage from the timing controller according to each of the plurality of flicker preventive signals generated thus to generate a plurality of modulated gate on voltages; a level shifter unit for changing the plurality of clock signals from the timing controller according to the plurality of modulated gate on voltages from the gate pulse modulation unit and a gate low voltage from the timing controller to generate a plurality of level shifted and modulated clock signals; and a gate driver for driving gate lines on the liquid crystal panel according to the a plurality of level shifted and modulated clock signals.
    • 本发明涉及一种用于驱动液晶显示装置的电路,其中不使用多闪烁防止信号FLK,而仅使用单个防闪烁信号FLK来减少定时控制器和电平转换器的引脚数。 用于驱动液晶显示装置的电路包括具有用于显示图像的多个像素区域的液晶面板,用于产生一个防闪烁信号的定时控制器和多个时钟信号和门控制信号,以控制液晶显示装置的驱动定时 栅极驱动器,门脉冲调制单元,用于逻辑地操作来自定时控制器的一个防闪烁信号和多个时钟信号,以产生多个防闪烁信号,并且根据每个的时序控制器调制栅极高电压 多个防止闪烁信号产生,从而产生多个调制栅极电压; 电平移位器单元,用于根据来自门脉冲调制单元的多个调制栅极导通电压和来自定时控制器的栅极低电压,从定时控制器改变多个时钟信号,以产生多个电平移位和调制时钟信号 ; 以及用于根据多个电平移位和调制的时钟信号在液晶面板上驱动栅极线的栅极驱动器。
    • 8. 发明授权
    • Semiconductor device and method for manufacturing the same
    • 半导体装置及其制造方法
    • US08178441B2
    • 2012-05-15
    • US11186396
    • 2005-07-21
    • Seok-Su Kim
    • Seok-Su Kim
    • H01L21/44H01L21/4763
    • H01L21/76802H01L21/28525H01L21/76801H01L21/76837H01L21/823425
    • A method for manufacturing a semiconductor device includes forming a gate insulating layer, a gate and a protective layer on a semiconductor substrate, forming a spacer on lateral sides of the protective layer and the gate, forming one or more junction regions in the semiconductor substrate at sides of the gate, partially filling a gap between adjacent gates by selectively forming a conductive layer on an exposed portion of the semiconductor substrate between the adjacent gates, forming an insulating layer over the semiconductor substrate so as to fill a full height of the gap between the adjacent gates, and forming a contact hole partially exposing the conductive layer by etching the insulating layer.
    • 一种半导体器件的制造方法包括在半导体衬底上形成栅极绝缘层,栅极和保护层,在保护层和栅极的侧面形成间隔物,在半导体衬底中形成一个或多个结区域 通过在相邻栅极之间的半导体衬底的暴露部分上选择性地形成导电层,在相邻栅极之间部分地填充间隙,在半导体衬底上形成绝缘层,以便填充半导体衬底之间的间隙的全高 并且通过蚀刻绝缘层形成部分暴露导电层的接触孔。
    • 10. 发明授权
    • Semiconductor device with a metal line and method of forming the same
    • 具有金属线的半导体器件及其形成方法
    • US07384865B2
    • 2008-06-10
    • US11313723
    • 2005-12-22
    • Seok-Su Kim
    • Seok-Su Kim
    • H01L21/283
    • H01L21/76801H01L21/76802
    • A method of forming a metal line in a semiconductor device includes: forming a lower insulation layer for insulation from the lower substrate; forming a first metal line at a certain region on the lower insulation layer; sequentially forming a first oxide layer, an FSG (Fluorine-doped Silicate Glass) layer, and a second oxide layer on the lower insulation layer and the first metal line; removing the first oxide layer, the FSG layer, and the second oxide layer so as to expose the first metal line; forming an upper insulation layer on the lower insulation layer and the first metal line; forming a contact hole by etching the upper insulation layer to a degree that the first metal line is exposed; and forming a second metal line by depositing a metal material in the contact hole.
    • 在半导体器件中形成金属线的方法包括:形成用于与下基板绝缘的下绝缘层; 在下绝缘层上的某一区域形成第一金属线; 顺序地形成第一氧化物层,FSG(氟掺杂硅酸盐玻璃)层和第二氧化物层在下绝缘层和第一金属线上; 去除第一氧化物层,FSG层和第二氧化物层,以暴露第一金属线; 在所述下绝缘层和所述第一金属线上形成上绝缘层; 通过将上部绝缘层蚀刻到第一金属线露出的程度来形成接触孔; 以及通过在所述接触孔中沉积金属材料形成第二金属线。