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1. 发明授权

US08537610B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08537610B2
公开(公告)日：2013-09-17
申请号：US12834418
申请日：2010-07-12
申请人： Serguei Okhonin , Viktor I Koldiaev , Mikhail Nagoga , Yogesh Luthra
发明人： Serguei Okhonin , Viktor I Koldiaev , Mikhail Nagoga , Yogesh Luthra
IPC分类号： G11C16/04 , G11C11/24 , H01L29/788
CPC分类号： H01L27/10844 , G11C11/39 , G11C11/403 , G11C11/404 , G11C16/10 , G11C2211/4016 , H01L21/76831 , H01L21/76877 , H01L21/823475 , H01L27/1023 , H01L27/108 , H01L27/10802 , H01L29/66477 , H01L29/7841
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为包括第一区域和第二区域的装置。该装置还可以包括设置在第一区域和第二区域之间并且电容耦合到多个字线的主体区域，其中多个字线中的每一个电容耦合到身体区域的不同部分。

2. 发明授权

US08748959B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08748959B2
公开(公告)日：2014-06-10
申请号：US12751245
申请日：2010-03-31
申请人： Michael A. Van Buskirk , Christian Caillat , Viktor I Koldiaev , Jungtae Kwon , Pierre C. Fazan
发明人： Michael A. Van Buskirk , Christian Caillat , Viktor I Koldiaev , Jungtae Kwon , Pierre C. Fazan
IPC分类号： H01L27/108 , H01L21/762
CPC分类号： H01L29/1095 , H01L21/76264 , H01L27/108 , H01L27/10802 , H01L27/10891 , H01L29/7841
摘要： A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.
摘要翻译：公开了一种半导体存储器件。在一个特定的示例性实施例中，半导体存储器件包括以行和列的阵列排列的多个存储器单元。每个存储单元可以包括连接到沿第一取向延伸的源极线的第一区域。每个存储单元还可以包括连接到延伸第二取向的位线的第二区域。每个存储器单元还可以包括与字线间隔开并且电容耦合到字线的主体区域，其中所述主体区域电浮动并且设置在所述第一区域和所述第二区域之间。半导体器件还可以包括在第一取向上延伸的第一阻挡壁和在第二取向上延伸并与第一阻挡壁相交的第二阻挡壁，以形成配置成容纳多个存储单元中的每一个的沟槽区。

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