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1. 发明授权

US08537610B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08537610B2
公开(公告)日：2013-09-17
申请号：US12834418
申请日：2010-07-12
申请人： Serguei Okhonin , Viktor I Koldiaev , Mikhail Nagoga , Yogesh Luthra
发明人： Serguei Okhonin , Viktor I Koldiaev , Mikhail Nagoga , Yogesh Luthra
IPC分类号： G11C16/04 , G11C11/24 , H01L29/788
CPC分类号： H01L27/10844 , G11C11/39 , G11C11/403 , G11C11/404 , G11C16/10 , G11C2211/4016 , H01L21/76831 , H01L21/76877 , H01L21/823475 , H01L27/1023 , H01L27/108 , H01L27/10802 , H01L29/66477 , H01L29/7841
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为包括第一区域和第二区域的装置。该装置还可以包括设置在第一区域和第二区域之间并且电容耦合到多个字线的主体区域，其中多个字线中的每一个电容耦合到身体区域的不同部分。

2. 发明申请

US20110007578A1 TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US20110007578A1
公开(公告)日：2011-01-13
申请号：US12834418
申请日：2010-07-12
申请人： Serguei Okhonin , Viktor I. Koldiaev , Mikhail Nagoga , Yogesh Luthra
发明人： Serguei Okhonin , Viktor I. Koldiaev , Mikhail Nagoga , Yogesh Luthra
IPC分类号： G11C5/14 , H01L27/108
CPC分类号： H01L27/10844 , G11C11/39 , G11C11/403 , G11C11/404 , G11C16/10 , G11C2211/4016 , H01L21/76831 , H01L21/76877 , H01L21/823475 , H01L27/1023 , H01L27/108 , H01L27/10802 , H01L29/66477 , H01L29/7841
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为包括第一区域和第二区域的装置。该装置还可以包括设置在第一区域和第二区域之间并且电容耦合到多个字线的主体区域，其中多个字线中的每一个电容耦合到身体区域的不同部分。

3. 发明申请

US20100271857A1 TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US20100271857A1
公开(公告)日：2010-10-28
申请号：US12768322
申请日：2010-04-27
申请人： Yogesh Luthra , Serguei Okhonin , Mikhail Nagoga
发明人： Yogesh Luthra , Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： H01L27/0664 , G11C5/025 , G11C5/06 , G11C5/063 , G11C7/00 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/4094 , G11C2211/4016 , H01L29/7302 , H01L29/732
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为用于偏置直接注入半导体存储器件的方法。该方法可以包括经由位线将第一电压电势施加到第一N掺杂区域，并且经由源极线将第二电压电势施加到第二N掺杂区域。该方法还可以包括将第三电压电位施加到字线，其中字线与电浮置并且设置在第一N掺杂区域和第二N掺杂区域之间的体区间隔开并且电容耦合。该方法还可以包括经由载体注入管线向P型衬底施加第四电压电位。

4. 发明授权

US08508970B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08508970B2
公开(公告)日：2013-08-13
申请号：US12768322
申请日：2010-04-27
申请人： Yogesh Luthra , Serguei Okhonin , Mikhail Nagoga
发明人： Yogesh Luthra , Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C5/06
CPC分类号： H01L27/0664 , G11C5/025 , G11C5/06 , G11C5/063 , G11C7/00 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/4094 , G11C2211/4016 , H01L29/7302 , H01L29/732
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device. The method may comprise applying a first voltage potential to a first N-doped region via a bit line and applying a second voltage potential to a second N-doped region via a source line. The method may also comprise applying a third voltage potential to a word line, wherein the word line is spaced apart from and capacitively coupled to a body region that is electrically floating and disposed between the first N-doped region and the second N-doped region. The method may further comprise applying a fourth voltage potential to a P-type substrate via a carrier injection line.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，可以将技术实现为用于偏置直接注入半导体存储器件的方法。该方法可以包括经由位线将第一电压电势施加到第一N掺杂区域，并且经由源极线将第二电压电势施加到第二N掺杂区域。该方法还可以包括将第三电压电位施加到字线，其中字线与电浮置并且设置在第一N掺杂区域和第二N掺杂区域之间的体区间隔开并且电容耦合。该方法还可以包括经由载体注入管线向P型衬底施加第四电压电位。

5. 发明授权

US07933142B2 Semiconductor memory cell and array using punch-through to program and read same 有权
标题翻译：半导体存储单元和阵列使用穿通来编程和读取相同
公开(公告)号：US07933142B2
公开(公告)日：2011-04-26
申请号：US11796935
申请日：2007-04-30
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.
摘要翻译：一种集成电路器件（例如逻辑或分立存储器件），包括一个包括穿通型晶体管的存储单元，其中该晶体管包括一个源极区，一个漏极区，一个栅极，一个栅极绝缘体，以及一个具有存储节点至少部分地位于栅极绝缘体的正下方。存储单元包括代表身体区域中的存储节点中的电荷量的至少两个数据状态。第一电路耦合到存储单元的穿通模式晶体管，以：（1）产生第一和第二组写入控制信号，以及（2a）将第一组写入控制信号施加到晶体管以写入第一数据状态，并且（2b）将第二组写入控制信号施加到晶体管以在存储器单元中写入第二数据状态。响应于第一组写入控制信号，穿通模式晶体管经由冲击电离至少提供身体区域中的第一电荷。晶体管可以设置在体型衬底或SOI型衬底上。

6. 发明授权

US07606066B2 Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same 有权
标题翻译：具有电浮体晶体管的存储单元和存储单元阵列及其操作方法
公开(公告)号：US07606066B2
公开(公告)日：2009-10-20
申请号：US11509188
申请日：2006-08-24
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C11/34
CPC分类号： G11C11/409 , G11C11/404 , G11C11/4067 , G11C11/4076 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： A technique of writing, programming, holding, maintaining, sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In one aspect, the present inventions are directed to techniques to control and/or operate a semiconductor memory cell (and memory cell array having a plurality of such memory cells as well as an integrated circuit device including a memory cell array) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques of the present inventions may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the present inventions may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
摘要翻译：写入，编程，保持，维护，采样，感测，读取和/或确定存储器单元阵列的存储器单元的数据状态（例如，具有多个存储器单元的存储器单元阵列的技术）电浮体晶体管）。一方面，本发明涉及用于控制和/或操作半导体存储单元（以及具有多个这样的存储单元的存储单元阵列以及包括存储单元阵列的集成电路器件）的技术，该半导体存储单元具有一个或多个电浮动体晶体管，其中电荷存储在电浮体晶体管的体区中。本发明的技术可以采用双极晶体管电流来控制，写入和/或读取这种存储单元中的数据状态。在这方面，本发明可以采用双极晶体管电流来控制，写入和/或读取存储单元的电浮体晶体管中的数据状态。

7. 发明授权

US08659948B2 Techniques for reading a memory cell with electrically floating body transistor 有权
标题翻译：用电浮体晶体管读取存储单元的技术
公开(公告)号：US08659948B2
公开(公告)日：2014-02-25
申请号：US13336805
申请日：2011-12-23
申请人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
发明人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
IPC分类号： G11C16/04
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括基本上由一个晶体管组成的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。该装置包括耦合到该存储单元的数据检测电路。数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

8. 发明申请

US20110194363A1 SEMICONDUCTOR MEMORY CELL AND ARRAY USING PUNCH-THROUGH TO PROGRAM AND READ SAME 有权
标题翻译：半导体存储单元和阵列使用PUNCH-THROUGH编程和读取它们
公开(公告)号：US20110194363A1
公开(公告)日：2011-08-11
申请号：US13092704
申请日：2011-04-22
申请人： Serguei Okhonin , Mikhail Nagoga
发明人： Serguei Okhonin , Mikhail Nagoga
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate.
摘要翻译：一种集成电路器件（例如逻辑或分立存储器件），包括一个包括穿通型晶体管的存储器单元，其中该晶体管包括一个源极区，一个漏极区，一个栅极，一个栅极绝缘体以及一个具有存储节点至少部分地位于栅极绝缘体的正下方。存储单元包括代表身体区域中的存储节点中的电荷量的至少两个数据状态。第一电路耦合到存储单元的穿通模式晶体管，以：（1）产生第一和第二组写入控制信号，以及（2a）将第一组写入控制信号施加到晶体管以写入第一数据状态，并且（2b）将第二组写入控制信号施加到晶体管以在存储器单元中写入第二数据状态。响应于第一组写入控制信号，穿通模式晶体管经由冲击电离至少提供身体区域中的第一电荷。晶体管可以设置在体型衬底或SOI型衬底上。

9. 发明申请

US20090080244A1 Refreshing Data of Memory Cells with Electrically Floating Body Transistors 有权
标题翻译：具有电浮体晶体管的存储单元刷新数据
公开(公告)号：US20090080244A1
公开(公告)日：2009-03-26
申请号：US12212326
申请日：2008-09-17
申请人： Eric Carman , Mikhail Nagoga , Serguei Okhonin
发明人： Eric Carman , Mikhail Nagoga , Serguei Okhonin
IPC分类号： G11C11/34
CPC分类号： G11C11/4096 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括一个包括一个晶体管的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。存储在设备的存储单元中的数据可以在单个时钟周期内刷新。

10. 发明申请

US20090016101A1 Reading Technique for Memory Cell With Electrically Floating Body Transistor 有权
标题翻译：具有电浮体晶体管的存储单元的读取技术
公开(公告)号：US20090016101A1
公开(公告)日：2009-01-15
申请号：US12130011
申请日：2008-05-30
申请人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
发明人： Serguei Okhonin , Mikhail Nagoga , Cedric Bassin
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.
摘要翻译：描述了包括其的电路的半导体器件及其操作方法。该器件包括基本上由一个晶体管组成的存储单元。晶体管包括栅极，电浮体区域，以及邻近身体区域的源极区域和漏极区域。该装置包括耦合到该存储单元的数据检测电路。数据检测电路包括耦合到栅极区域的字线和耦合到源极区域或漏极区域的位输出。

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