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    • 5. 发明授权
    • Apparatus for developing and verifying system-on-chip for internet phone
    • 用于互联网电话开发和验证片上系统的设备
    • US07526679B2
    • 2009-04-28
    • US11183673
    • 2005-07-18
    • Woon-Seob SoDo-Young KimYoung-Sun Kim
    • Woon-Seob SoDo-Young KimYoung-Sun Kim
    • G06F11/00
    • G06F11/267
    • Provided is an apparatus for developing and verifying a system-on-chip for an Internet phone. The object of the present invention is to provide the system-on-chip developing and verifying apparatus for the Internet phone, which can develop and verify the system-on-chip simultaneously by integrating an Advanced RISC Machine(ARM) core module, a field programmable gate array (FPGA), a peripheral interface and the system-on-chip. The apparatus includes an ARM core module performing a core processor function, a peripheral interface including a memory and many external input/output devices, a FPGA controlling the ARM core module and performing a control function for connecting the ARM core module and the peripheral interface, and a system-on-chip integrating the functions of the ARM core module and the FPGA.
    • 提供了一种用于开发和验证因特网电话的片上系统的装置。 本发明的目的是提供一种用于互联网电话的系统级芯片开发和验证装置,其可以通过集成高级RISC机(ARM)核心模块,现场 可编程门阵列(FPGA),外围接口和片上系统。 该装置包括执行核心处理器功能的ARM核心模块,包括存储器和许多外部输入/输出设备的外围接口,控制ARM核心模块的FPGA并执行用于连接ARM核心模块和外围接口的控制功能, 以及集成ARM内核模块和FPGA功能的片上系统。
    • 10. 发明授权
    • Dual port random access memory matching circuit for versa module Europe
bus (VMEbus)
    • 双端口随机存取存储器匹配电路,用于反模块欧洲总线(VMEbus)
    • US5822769A
    • 1998-10-13
    • US742894
    • 1996-11-01
    • Woon-Seob SoJin-Tae Kim
    • Woon-Seob SoJin-Tae Kim
    • G06F13/40G06F13/00G06F12/00
    • G06F13/4059
    • A dual port random access memory (RAM) matching circuit for a Versa Module Europe bus (VMEbus) which makes it possible to have a higher capacity when transmitting and receiving data by using a RAM which is possible to bidirectionally access during a communication between processors using a VMEbus of an electronic switching system. The dual port RAM matching circuit includes a dual port RAM for bidirectionally outputting/inputting a data in accordance with an address and a control signal, an address matching unit for selecting first through sixteenth addresses from a local system or first through sixteenth addresses from a VMEbus in accordance with the control signal, and a data matching unit for selecting 0-th through thirty first CPU data or 0-th through thirty first VMEbus data from the local system in accordance with the control signal from the control bus, and for checking a parity during a data transmission and receiving operation. The dual port RAM matching circuit further includes a control signal matching unit for selecting either the control signal from the local system or the control signal from the VMEbus in accordance with the control signal from the control bus and for outputting the selected control signal to the control bus, and a control signal generator for receiving an address information signal and a clock signal from the local system, and an address information signal from the VMEbus, and outputting control signals to the control bus.
    • 一种用于Versa模块欧洲总线(VMEbus)的双端口随机存取存储器(RAM)匹配电路,使得可以通过使用RAM进行发送和接收数据时具有更高的容量,RAM可以在处理器之间的通信期间双向访问 电子交换系统的VMEbus。 双端口RAM匹配电路包括用于根据地址和控制信号双向输出/输入数据的双端口RAM,用于从本地系统中选择第一至第十六地址的地址匹配单元或从VME总线 根据控制信号,以及数据匹配单元,用于根据来自控制总线的控制信号从本地系统中选择0到30个第一CPU数据或第0到第30个第一VME总线数据,并且用于检查 在数据发送和接收操作期间的奇偶校验。 双端口RAM匹配电路还包括控制信号匹配单元,用于根据来自控制总线的控制信号选择来自本地系统的控制信号或来自VME总线的控制信号,并将所选择的控制信号输出到控制 总线和控制信号发生器,用于从本地系统接收地址信息信号和时钟信号,以及来自VMEbus的地址信息信号,并将控制信号输出到控制总线。