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    • 3. 发明授权
    • CCD image sensors having multiple lateral overflow drain regions for a horizontal shift register
    • 具有用于水平移位寄存器的多个横向溢出漏极区域的CCD图像传感器
    • US08605187B2
    • 2013-12-10
    • US12475825
    • 2009-06-01
    • Shen WangEric J. MeisenzahlDavid N. Nichols
    • Shen WangEric J. MeisenzahlDavid N. Nichols
    • H01L27/15H04N5/335
    • H01L27/14887
    • A charge-coupled device (CCD) image sensor includes a layer of a semiconductor material having a first conductivity type. A horizontal CCD channel region of a second conductivity type is disposed in the layer of the semiconductor material. The horizontal CCD channel region includes multiple phases that are used to shift photo-generated charge through the horizontal CCD channel region. Distinct overflow drain regions are disposed in the layer of semiconducting material, with an overflow drain region electrically connected to only one particular phase of the horizontal CCD channel region. A buffer region of the second conductivity type can be used to electrically connect each overflow drain to the one particular phase of the horizontal CCD channel. Multiple barrier regions are disposed in the layer of semiconductor material, with each barrier region disposed between each overflow drain and the one particular phase electrically connected to the drain.
    • 电荷耦合器件(CCD)图像传感器包括具有第一导电类型的半导体材料层。 第二导电类型的水平CCD沟道区设置在半导体材料的层中。 水平CCD通道区域包括用于将光电荷移动通过水平CCD通道区域的多个相位。 不同的溢出漏极区域设置在半导体材料层中,溢出漏极区域仅电连接到水平CCD沟道区域的一个特定相位。 可以使用第二导电类型的缓冲区域将每个溢出漏极电连接到水平CCD通道的一个特定相位。 多个屏障区域设置在半导体材料层中,每个屏障区域设置在每个溢流漏极和电连接到漏极的一个特定相之间。
    • 8. 发明申请
    • CCD IMAGE SENSORS WITH VARIABLE OUTPUT GAINS IN AN OUTPUT CIRCUIT
    • CCD图像传感器在输出电路中具有可变输出增益
    • US20110074996A1
    • 2011-03-31
    • US12568696
    • 2009-09-29
    • Shen WangChristopher Parks
    • Shen WangChristopher Parks
    • H04N5/335
    • H04N5/37213
    • An output circuit in a charge-coupled device (CCD) image sensor includes a charge-to-voltage conversion region, a gain control transistor connected to the charge-to-voltage conversion region and a reset transistor connected in series with the gain control transistor. One or more additional gain control transistors can be connected between the reset transistor and the gain control transistor. The one or more gain control transistors are used to set a capacitance of the charge-to-voltage conversion region to two or more difference capacitance levels. For each capacitance level, a reset voltage and a signal voltage are measured from the charge-to-voltage conversion region. A signal processing device computes multiple signal values for a single charge packet using the measured reset and signal voltages. The signal processing device selects one of the multiple signal values to be the signal value for the pixel.
    • 电荷耦合器件(CCD)图像传感器中的输出电路包括电荷 - 电压转换区域,连接到电荷 - 电压转换区域的增益控制晶体管和与增益控制晶体管串联连接的复位晶体管 。 一个或多个附加的增益控制晶体管可以连接在复位晶体管和增益控制晶体管之间。 一个或多个增益控制晶体管用于将电荷 - 电压转换区域的电容设置为两个或更多个不同的电容电平。 对于每个电容电平,从电荷到电压转换区域测量复位电压和信号电压。 信号处理装置使用所测量的复位和信号电压来计算单个电荷包的多个信号值。 信号处理装置选择多个信号值中的一个作为像素的信号值。
    • 9. 发明授权
    • Semiconductor layout design apparatus, semiconductor layout design method and computer readable medium
    • 半导体布局设计设备,半导体布局设计方法和计算机可读介质
    • US07831947B2
    • 2010-11-09
    • US11941739
    • 2007-11-16
    • Shen WangTetsuaki UtsumiMizue Sekine
    • Shen WangTetsuaki UtsumiMizue Sekine
    • G06F17/50
    • G06F17/5072
    • A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The block global placement part configured to roughly place the plurality of blocks in a placement region on a semiconductor substrate. The cell placement setting part configured to set placement positions of the macrocells in the block based on a positioning relationship with the other block and the number of the wiring connections with the other block with respect to each of the plurality of blocks roughly placed by the block global placement part.
    • 半导体布局设计装置具有块间连接信息提取部分,块全局放置部分和单元布置设置部分。 块间​​连接信息提取部,被配置为基于网表,库信息,平面图信息和技术信息来提取包括标准单元的多个块和宏小区之间的布线连接数。 块全局放置部分被配置为将多个块粗略地放置在半导体衬底上的放置区域中。 所述单元布置设置部分被配置为基于与所述另一块的定位关系以及与所述另一块相对于由所述块大致放置的所述多个块中的每一个的所述布线连接的数量来设置所述块中的所述宏单元的布局位置 全球放置部分。
    • 10. 发明申请
    • SEMICONDUCTOR LAYOUT DESIGN APPARATUS, SEMICONDUCTOR LAYOUT DESIGN METHOD AND COMPUTER READABLE MEDIUM
    • 半导体布局设计设备,半导体布局设计方法和计算机可读介质
    • US20080120582A1
    • 2008-05-22
    • US11941748
    • 2007-11-16
    • Shen WangTetsuaki UtsumiMizue Sekine
    • Shen WangTetsuaki UtsumiMizue Sekine
    • G06F17/50
    • G06F17/5072G06F17/5081
    • A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The cell initial placement part configured to initially place the standard cells and the macrocells in an placement region to generate an initial floor plan. The evaluation value calculating part configured to calculate an evaluation value of the floor plan based on distances between a plurality of blocks including the standard cells and the macrocells initially placed by the cell initial placement part and the extracted number of the wiring connections between a plurality of blocks.
    • 半导体布局设计装置具有块间连接信息提取部分,单元初始放置部分和评估值。 块间​​连接信息提取部,被配置为基于网表,库信息,平面图信息和技术信息来提取包括标准单元的多个块和宏小区之间的布线连接数。 单元初始放置部分被配置为最初将标准单元和宏单元放置在放置区域中以生成初始平面图。 所述评价值运算部被配置为基于包括所述标准单元的多个块与由所述单元初始化配置部开始配置的宏单元之间的距离以及所提取的多个 块。