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1. 发明授权

US07576551B2 Test socket and test board for wafer level semiconductor testing 有权
标题翻译：用于晶圆级半导体测试的测试插座和测试板
公开(公告)号：US07576551B2
公开(公告)日：2009-08-18
申请号：US11902309
申请日：2007-09-20
申请人： Sheng-Feng Lu , Shih-Ming Chen , Chien-Pang Lin , Ming-Hsun Sung
发明人： Sheng-Feng Lu , Shih-Ming Chen , Chien-Pang Lin , Ming-Hsun Sung
IPC分类号： G01R31/26
CPC分类号： G01R1/0408 , G01R1/0466 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2924/15311 , H01L2924/00
摘要： A test board for wafer level semiconductor testing is disclosed. The test board comprises a plurality of wires and microelectronic devices; and a plurality of test sockets on an upper surface of the test board. Each test socket comprises: a base member configured for attachment to the test board with a first set of screws, wherein the base member has a central opening exposing a portion of the underlying test board; an anisotropic conductive film disposed within the central opening of the base member; a chip to be tested, disposed on the anisotropic conductive film within the central opening of the base member; and a cover member overlying the chip, attached to the base member with a second set of screws.
摘要翻译：公开了一种用于晶片级半导体测试的测试板。测试板包括多根导线和微电子器件; 以及在测试板的上表面上的多个测试插座。每个测试插座包括：基座构件，其构造成用第一组螺钉附接到测试板，其中所述基座构件具有暴露所述底层测试板的一部分的中心开口; 设置在所述基底构件的中心开口内的各向异性导电膜; 待测试的芯片，设置在基底构件的中心开口内的各向异性导电膜上; 以及覆盖所述芯片的盖构件，以第二组螺钉附接到所述基座构件。

2. 发明申请

US20090079461A1 Test socket and test board for wafer level semiconductor testing 有权
公开(公告)号：US20090079461A1
公开(公告)日：2009-03-26
申请号：US11902309
申请日：2007-09-20
申请人： Sheng-Feng Lu , Shih-Ming Chen , Chien-Pang Lin , Ming-Hsun Sung
发明人： Sheng-Feng Lu , Shih-Ming Chen , Chien-Pang Lin , Ming-Hsun Sung
IPC分类号： G01R1/04 , G01R31/26
CPC分类号： G01R1/0408 , G01R1/0466 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2924/15311 , H01L2924/00
摘要： A test board for wafer level semiconductor testing is disclosed. The test board comprises a plurality of wires and microelectronic devices; and a plurality of test sockets on an upper surface of the test board. Each test socket comprises: a base member configured for attachment to the test board with a first set of screws, wherein the base member has a central opening exposing a portion of the underlying test board; an anisotropic conductive film disposed within the central opening of the base member; a chip to be tested, disposed on the anisotropic conductive film within the central opening of the base member; and a cover member overlying the chip, attached to the base member with a second set of screws.

3. 发明授权

US10923011B2 Bistable display device and driving circuit 有权
公开(公告)号：US10923011B2
公开(公告)日：2021-02-16
申请号：US16661992
申请日：2019-10-23
申请人： Tzu-Yi Wu , Ming-Hsun Sung
发明人： Tzu-Yi Wu , Ming-Hsun Sung
IPC分类号： G06F3/038 , G09G5/00 , G09G5/10 , G09G3/20
摘要： The disclosure provides a bistable display device and a driving circuit. The bistable display device includes a display panel and the above-described driving circuit, wherein the driving circuit includes a source driver, a first image buffer, a second image buffer, and a timing controller. The source driver is coupled to the display panel to drive the display panel according to a pixel signal. The timing controller is coupled to the first image buffer, the second image buffer, and the source driver. The timing controller alternately selects a first image signal temporarily stored in the first image buffer and a second image signal temporarily stored in the second image buffer as a current image signal and a previous image signal. The timing controller performs a look-up mechanism based on the current image signal and the previous image signal to generate the pixel signal.

4. 发明授权

US10923081B2 Timing controller, display apparatus, and operation method thereof 有权
公开(公告)号：US10923081B2
公开(公告)日：2021-02-16
申请号：US16408451
申请日：2019-05-09
申请人： Tzu-Yi Wu , Ming-Hsun Sung
发明人： Tzu-Yi Wu , Ming-Hsun Sung
IPC分类号： G09G5/18 , G09G5/00 , G09G3/36 , G09G3/20
摘要： A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

5. 发明申请

US20200258476A1 TIMING CONTROLLER, DISPLAY APPARATUS, AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：US20200258476A1
公开(公告)日：2020-08-13
申请号：US16408451
申请日：2019-05-09
申请人： Tzu-Yi Wu , Ming-Hsun Sung
发明人： Tzu-Yi Wu , Ming-Hsun Sung
IPC分类号： G09G5/18 , G09G5/00 , G09G3/20 , G09G3/36
摘要： A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

6. 发明授权

US08051339B2 Data preserving method and data accessing method for non-volatile memory 有权
标题翻译：用于非易失性存储器的数据保存方法和数据访问方法
公开(公告)号：US08051339B2
公开(公告)日：2011-11-01
申请号：US12015484
申请日：2008-01-16
申请人： Ming-Hsun Sung , Yu-Lin Hsieh
发明人： Ming-Hsun Sung , Yu-Lin Hsieh
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.
摘要翻译：提供了一种用于非易失性存储器的数据保存方法和数据访问方法。在数据保存方法中，根据纠错码（ECC）检查数据，以获得数据的错误位数。当错误位数大于阈值时，数据从第一存储器单元移动到第二存储器单元，并根据ECC进行校正。从而提高了非易失性存储器的数据稳定性。

7. 发明授权

US07675361B2 Class-D amplifier and multi-level output signal generated method thereof 失效
标题翻译： D类放大器及其多电平输出信号产生方法
公开(公告)号：US07675361B2
公开(公告)日：2010-03-09
申请号：US12025055
申请日：2008-02-04
申请人： Lee-Chun Guo , Ming-Hsun Sung
发明人： Lee-Chun Guo , Ming-Hsun Sung
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.
摘要翻译：提供了D类放大器和一种产生其多电平输出信号的方法。 D类放大器包括控制逻辑电路和输出模块。控制逻辑电路分析输入信号的幅度以产生电压修正信号。电源根据电压修正信号提供电压。控制逻辑电路根据输入信号产生控制信号。输出模块根据电压和控制信号产生输出信号来驱动负载。换句话说，通过修改电压来增加输出信号幅度的分辨率，然后增加信噪比。

8. 发明授权

US11509655B2 Authentication system and authentication method 有权
公开(公告)号：US11509655B2
公开(公告)日：2022-11-22
申请号：US16894889
申请日：2020-06-08
申请人： Yao-Te Fang , Ming-Hsun Sung
发明人： Yao-Te Fang , Ming-Hsun Sung
IPC分类号： H04L29/06 , H04L9/40 , H04W12/06 , G06F21/44 , H04L9/32 , H04L9/06 , H04W12/041
摘要： An authentication system and an authentication method are provided. The electronic device of the authentication system includes a controller, a processor and a key module, wherein the processor performs an application program. In a binding phase, the application device generates a digest file according to key factor information and a selection strategy, and stores the digest file in a digest table of the electronic device. In a checking phase, the application program determines whether the controller corresponds to a binding device according to the digest file and the key factor information. If the controller corresponded to the binding device, in an authentication phase, the controller performs an authentication operation of a U2F service with a server device according to the digest file corresponding to the binding device in response to a pressing of the key module.

9. 发明申请

US20090146737A1 CLASS-D AMPLIFIER AND MULTI-LEVEL OUTPUT SIGNAL GENERATED METHOD THEREOF 失效
标题翻译： CLASS-D放大器和多级输出信号生成方法
公开(公告)号：US20090146737A1
公开(公告)日：2009-06-11
申请号：US12025055
申请日：2008-02-04
申请人： Lee-Chun Guo , Ming-Hsun Sung
发明人： Lee-Chun Guo , Ming-Hsun Sung
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.
摘要翻译：提供了D类放大器和一种产生其多电平输出信号的方法。 D类放大器包括控制逻辑电路和输出模块。控制逻辑电路分析输入信号的幅度以产生电压修正信号。电源根据电压修正信号提供电压。控制逻辑电路根据输入信号产生控制信号。输出模块根据电压和控制信号产生输出信号来驱动负载。换句话说，通过修改电压来增加输出信号幅度的分辨率，然后增加信噪比。

10. 发明申请

US20090125764A1 DATA PRESERVING METHOD AND DATA ACCESSING METHOD FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的数据保存方法和数据访问方法
公开(公告)号：US20090125764A1
公开(公告)日：2009-05-14
申请号：US12015484
申请日：2008-01-16
申请人： Ming-Hsun Sung , Yu-Lin Hsieh
发明人： Ming-Hsun Sung , Yu-Lin Hsieh
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.
摘要翻译：提供了一种用于非易失性存储器的数据保存方法和数据访问方法。在数据保存方法中，根据纠错码（ECC）检查数据，以获得数据的错误位数。当错误位数大于阈值时，数据从第一存储器单元移动到第二存储器单元，并根据ECC进行校正。从而提高了非易失性存储器的数据稳定性。

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