专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08478224B2 Mobile communication terminal device 有权
标题翻译：移动通信终端设备
公开(公告)号：US08478224B2
公开(公告)日：2013-07-02
申请号：US12838467
申请日：2010-07-18
申请人： Shigemasa Shiota , Kunihiro Katayama , Shinichi Fukasawa , Takeo Kon , Seiji Kobayashi
发明人： Shigemasa Shiota , Kunihiro Katayama , Shinichi Fukasawa , Takeo Kon , Seiji Kobayashi
IPC分类号： H04B1/06 , H04B5/00
CPC分类号： H04B5/0056 , G06K7/0008 , G06K7/10207
摘要： A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.
摘要翻译：提供了即使在从电池电力下降操作电压之后，也可以连续使用通过非接触式通信的认证和结算功能的移动通信终端设备。只有当电池所需电力的供给丢失时，才能将安全控制器控制为低功耗运行的模式，并通过外部电磁场功率确保非接触式认证和结算功能。因此，即使在通过使用用于主要目的的通信功能的电池剩余容量丢失之后，也可以使用非接触式认证和结算功能。具体而言，实现以下方式：当从电池供给所需电力时，可以进行高性能，多功能的认证和结算处理，从而充分利用高速处理，大容量存储等这是安全控制器基本上由电池驱动的优点; 并且在电池剩余容量损失的异常情况下，可以进行最小的认证和结算处理。

2. 发明申请

US20110034124A1 MOBILE COMMUNICATION TERMINAL DEVICE 有权
标题翻译：移动通信终端设备
公开(公告)号：US20110034124A1
公开(公告)日：2011-02-10
申请号：US12838467
申请日：2010-07-18
申请人： Shigemasa SHIOTA , Kunihiro Katayama , Shinichi Fukasawa , Takeo Kon , Seiji Kobayashi
发明人： Shigemasa SHIOTA , Kunihiro Katayama , Shinichi Fukasawa , Takeo Kon , Seiji Kobayashi
IPC分类号： H04B5/00
CPC分类号： H04B5/0056 , G06K7/0008 , G06K7/10207
摘要： A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.
摘要翻译：提供了即使在从电池电力下降操作电压之后，也可以连续使用通过非接触式通信的认证和结算功能的移动通信终端设备。只有当电池所需电力的供给丢失时，才能将安全控制器控制为低功耗运行的模式，并通过外部电磁场功率确保非接触式认证和结算功能。因此，即使在通过使用用于主要目的的通信功能的电池剩余容量丢失之后，也可以使用非接触式认证和结算功能。具体而言，实现以下方式：当从电池供给所需电力时，可以进行高性能，多功能的认证和结算处理，从而充分利用高速处理，大容量存储等这是安全控制器基本上由电池驱动的优点; 并且在电池剩余容量损失的异常情况下，可以进行最小的认证和结算处理。

3. 发明授权

US08503235B2 Nonvolatile memory with faulty cell registration 失效
标题翻译：具有故障单元注册的非易失性存储器
公开(公告)号：US08503235B2
公开(公告)日：2013-08-06
申请号：US13298548
申请日：2011-11-17
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34 , G11C11/29
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

4. 发明申请

US20100177579A1 SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS 有权
标题翻译：具有故障细胞的半导体存储器件
公开(公告)号：US20100177579A1
公开(公告)日：2010-07-15
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C29/04
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

5. 发明申请

US20070168782A1 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US20070168782A1
公开(公告)日：2007-07-19
申请号：US11599388
申请日：2006-11-15
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

6. 发明授权

US06694460B2 Semiconductor memory device having deterioration determining function 失效
标题翻译：半导体存储器件具有劣化判定功能
公开(公告)号：US06694460B2
公开(公告)日：2004-02-17
申请号：US09794073
申请日：2001-02-28
申请人： Kunihiro Katayama , Takayuki Tamura , Masashi Naito , Shigemasa Shiota
发明人： Kunihiro Katayama , Takayuki Tamura , Masashi Naito , Shigemasa Shiota
IPC分类号： G11C2900
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/50 , G11C29/50012
摘要： The memory device has an electrically rewritable nonvolatile memory used as a storage medium. To promote even deterioration throughout the memory, the erasing time and writing time are measured, the influence of scatter of cells in the memory are eliminated on the basis of the resultant measurement values and a degree of deterioration is determined with a high accuracy, whereby a memory device of a high reliability and high efficiency is realized. In order to rewrite the nonvolatile memory, therefore, the memory measures erasing time and writing time, compares erasing time with stored reference time, compares the writing time from the comparison results, and determines the degree of deterioration from the correction results. Accordingly, control is possible such that, successively, the more heavily deteriorated part of the memory is used less frequently while the less deteriorated part is used more frequently.
摘要翻译：存储器件具有用作存储介质的电可重写非易失性存储器。为了在整个存储器中促进均匀劣化，测量擦除时间和写入时间，基于所得到的测量值消除存储器中的单元散射的影响，并且以高精度确定劣化程度，由此实现了高可靠性和高效率的存储器件。因此，为了重写非易失性存储器，存储器测量擦除时间和写入时间，将擦除时间与存储的参考时间进行比较，比较比较结果的写入时间，并根据校正结果确定劣化程度。因此，可以进行控制，使得随着使用较少劣化部分的频率越来越低，存储器的劣化部分越来越少使用。

7. 发明授权

US06542405B2 Semiconductor memory device having faulty cells 有权
公开(公告)号：US06542405B2
公开(公告)日：2003-04-01
申请号：US10105275
申请日：2002-03-26
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C1606
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

8. 发明授权

US07721165B2 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US07721165B2
公开(公告)日：2010-05-18
申请号：US11599388
申请日：2006-11-15
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

9. 发明授权

US06199187B1 External storage device and memory access control method thereof 有权
公开(公告)号：US06199187B1
公开(公告)日：2001-03-06
申请号：US09544609
申请日：2000-04-06
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： H03M1300
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N−1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N−th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N−1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N−th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N−th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e., simultaneously), error detection and error correction of the (2N+1)th sector data (next sector data to be read by the host computer) read out from one of the first computer and second computer can be performed in the error correcting means. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed thereby the time required for error detection and error correction can be reduced apparently (i.e., made transparent to the host computer 2) and memory access can be obtained.

10. 再颁专利

USRE45857E1 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：USRE45857E1
公开(公告)日：2016-01-19
申请号：US13475679
申请日：2012-05-18
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式