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1. 发明授权

US08478224B2 Mobile communication terminal device 有权
标题翻译：移动通信终端设备
公开(公告)号：US08478224B2
公开(公告)日：2013-07-02
申请号：US12838467
申请日：2010-07-18
申请人： Shigemasa Shiota , Kunihiro Katayama , Shinichi Fukasawa , Takeo Kon , Seiji Kobayashi
发明人： Shigemasa Shiota , Kunihiro Katayama , Shinichi Fukasawa , Takeo Kon , Seiji Kobayashi
IPC分类号： H04B1/06 , H04B5/00
CPC分类号： H04B5/0056 , G06K7/0008 , G06K7/10207
摘要： A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.
摘要翻译：提供了即使在从电池电力下降操作电压之后，也可以连续使用通过非接触式通信的认证和结算功能的移动通信终端设备。只有当电池所需电力的供给丢失时，才能将安全控制器控制为低功耗运行的模式，并通过外部电磁场功率确保非接触式认证和结算功能。因此，即使在通过使用用于主要目的的通信功能的电池剩余容量丢失之后，也可以使用非接触式认证和结算功能。具体而言，实现以下方式：当从电池供给所需电力时，可以进行高性能，多功能的认证和结算处理，从而充分利用高速处理，大容量存储等这是安全控制器基本上由电池驱动的优点; 并且在电池剩余容量损失的异常情况下，可以进行最小的认证和结算处理。

2. 发明申请

US20090144834A1 DATA PROCESSING CIRCUIT AND COMMUNICATION MOBILE TERMINAL DEVICE 审中-公开
标题翻译：数据处理电路和通信移动终端设备
公开(公告)号：US20090144834A1
公开(公告)日：2009-06-04
申请号：US12271099
申请日：2008-11-14
申请人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota , Takeo Kon
发明人： Yoshinori MOCHIZUKI , Masaharu Ukeda , Shigemasa Shiota , Takeo Kon
IPC分类号： H04L9/32 , H04M1/00 , G06F12/02
CPC分类号： G11C16/22 , G11C16/225
摘要： A data processing circuit includes a rewritable nonvolatile memory and a controller performing nonvolatile memory control and external interface control. A first detector and a second detector are employed to detect respectively whether the operation of the data processing circuit deviates from a first operating condition and a second operating condition, wherein the second operating condition is severer than the first operating condition. When the first detector detects deviation from the first operating condition, reset is instructed to the controller. When the second detector detects deviation from the second operating condition, the controller backs up an internal state and imposes a restriction on external access to a storage region of the nonvolatile memory. Accordingly, when operation of the microcontroller deviates from specific operating conditions within an operation guarantee range and performance degradation is exhibited, an unauthorized access to the data inside the microcontroller can be suppressed.
摘要翻译：数据处理电路包括可重写非易失性存储器和执行非易失性存储器控制和外部接口控制的控制器。采用第一检测器和第二检测器来检测数据处理电路的操作是否偏离第一操作条件和第二操作条件，其中第二操作条件比第一操作条件更严格。当第一检测器检测到与第一操作条件的偏差时，向控制器指示复位。当第二检测器检测到与第二操作条件的偏差时，控制器备份内部状态并对对非易失性存储器的存储区域的外部访问施加限制。因此，当微控制器的操作在操作保证范围内偏离特定操作条件并且表现出性能下降时，可以抑制对微控制器内的数据的未经授权的访问。

3. 再颁专利

USRE45857E1 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：USRE45857E1
公开(公告)日：2016-01-19
申请号：US13475679
申请日：2012-05-18
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

4. 发明授权

US08064257B2 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US08064257B2
公开(公告)日：2011-11-22
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

5. 发明授权

US06223311B1 Semiconductor memory device having deterioration determining function 有权
标题翻译：半导体存储器件具有劣化判定功能
公开(公告)号：US06223311B1
公开(公告)日：2001-04-24
申请号：US09432389
申请日：1999-11-02
申请人： Kunihiro Katayama , Takayuki Tamura , Masashi Naito , Shigemasa Shiota
发明人： Kunihiro Katayama , Takayuki Tamura , Masashi Naito , Shigemasa Shiota
IPC分类号： G11C2900
CPC分类号： G11C29/028 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016
摘要： In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction. According to the present invention, the substantial deterioration of each cell can be determined, and such control is possible that more deteriorated memory is used less frequently while less deteriorated memory is used more frequently. As a result, the reliability of the memory is improved, and the memory can have a longer service life.
摘要翻译：在使用电可重写非易失性存储器作为存储介质的存储装置中，为了使存储器均匀地劣化，测量擦除时间和写入时间，基于消除了存储器中的单元的散射的影响所得到的测量值，由此以高精度确定了相当程度的劣化，从而实际上获得了高可靠性和高效率的存储器件。为了重写可重写的非易失性存储器（1），提供了一种用于测量擦除时间和写入时间的装置，用于将擦除时间与存储的基准时间进行比较的装置，用于基于比较结果，以及根据校正结果确定劣化的方法。根据本发明，可以确定每个单元的实质性劣化，并且可以更频繁地使用较少劣化的存储器，因此可以更少地使用更恶化的存储器，并且可以进行这种控制。结果，提高了存储器的可靠性，并且存储器可以具有更长的使用寿命。

6. 发明授权

US5978941A Semiconductor memory device having deterioration determining function 失效
标题翻译：半导体存储器件具有劣化判定功能
公开(公告)号：US5978941A
公开(公告)日：1999-11-02
申请号：US913338
申请日：1997-09-11
申请人： Kunihiro Katayama , Takayuki Tamura , Masashi Naito , Shigemasa Shiota
发明人： Kunihiro Katayama , Takayuki Tamura , Masashi Naito , Shigemasa Shiota
IPC分类号： G11C16/14 , G11C16/34 , G11C29/50 , G11C29/52 , G11C29/00
CPC分类号： G11C16/3495 , G11C16/14 , G11C16/349 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C29/52 , G11C29/56012 , G11C16/04
摘要： In a memory device using an electrically rewritable nonvolatile memory as a storage medium, wherein, in order to allow the memory to deteriorate evenly, the erasing time and writing time are measured, the influence of scatter of cells in the memory being eliminated on the basis of the resultant measurement values, a substantial degree of deterioration being thereby determined with a high accuracy, whereby a memory device of a high reliability and a high efficiency is practically obtained. In order to rewrite an electrically rewritable nonvolatile memory (1), there are provided a means for measuring the erasing time and writing time, a means for comparing an erasing time with a stored reference time, a means for correcting writing time on the basis of the results of the comparison, and a means for determining deterioration on the basis of the results of the correction. According to the present invention, the substantial deterioration of each cell can be determined, and such control is possible that more deteriorated memory is used less frequently while less deteriorated memory is used more frequently. As a result, the reliability of the memory is improved, and the memory can have a longer service life.
摘要翻译： PCT No.PCT / JP95 / 00429 Sec。 371日期：1997年9月11日 102（e）1997年9月11日PCT 1995年3月15日PCT PCT。出版物WO96 / 28826 日期1996年9月19日在使用电可重写非易失性存储器作为存储介质的存储器件中，为了使存储器均匀地劣化，测量擦除时间和写入时间，存储器中的单元散射的影响基于所得到的测量值消除，从而以高精度确定了显着的劣化程度，从而实际上获得了高可靠性和高效率的存储器件。为了重写可重写的非易失性存储器（1），提供了一种用于测量擦除时间和写入时间的装置，用于将擦除时间与存储的基准时间进行比较的装置，用于基于比较结果，以及根据校正结果确定劣化的方法。根据本发明，可以确定每个单元的实质性劣化，并且可以更频繁地使用较少劣化的存储器，因此可以更少地使用更恶化的存储器，并且可以进行这种控制。结果，提高了存储器的可靠性，并且存储器可以具有更长的使用寿命。

7. 发明授权

US07721165B2 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US07721165B2
公开(公告)日：2010-05-18
申请号：US11599388
申请日：2006-11-15
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

8. 发明授权

US06199187B1 External storage device and memory access control method thereof 有权
公开(公告)号：US06199187B1
公开(公告)日：2001-03-06
申请号：US09544609
申请日：2000-04-06
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： H03M1300
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N−1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N−th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N−1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N−th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N−th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e., simultaneously), error detection and error correction of the (2N+1)th sector data (next sector data to be read by the host computer) read out from one of the first computer and second computer can be performed in the error correcting means. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed thereby the time required for error detection and error correction can be reduced apparently (i.e., made transparent to the host computer 2) and memory access can be obtained.

9. 发明授权

US07616485B2 Semiconductor memory device having faulty cells 失效
公开(公告)号：US07616485B2
公开(公告)日：2009-11-10
申请号：US11931881
申请日：2007-10-31
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

10. 发明授权

US06728138B2 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US06728138B2
公开(公告)日：2004-04-27
申请号：US10373872
申请日：2003-02-27
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C1606
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

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