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1. 发明授权

US09190145B2 Drive method for memory element and storage device using memory element 有权
标题翻译：使用存储元件的存储元件和存储设备的驱动方法
公开(公告)号：US09190145B2
公开(公告)日：2015-11-17
申请号：US13819247
申请日：2011-08-25
申请人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
发明人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
IPC分类号： G11C11/00 , G11C13/00 , H01L27/10
CPC分类号： G11C13/0069 , G11C13/0002 , G11C2213/79 , H01L27/101
摘要： In a drive method for a memory element that includes an insulating substrate, a first electrode and a second electrode provided on the insulating substrate, and an inter-electrode gap portion provided between the first electrode and the second electrode and having a gap of the order of nanometers where a phenomenon of a change in resistance value between the first and second electrodes occurs, and that can perform a transition from a predetermined low-resistance state to a predetermined high-resistance state and a transition from the high-resistance state to the low-resistance state, a current pulse is applied to the memory element by a constant current circuit upon the transition from the high-resistance state to the low-resistance state.
摘要翻译：在包括绝缘基板的存储元件的驱动方法中，设置在所述绝缘基板上的第一电极和第二电极以及设置在所述第一电极和所述第二电极之间并且具有所述第一电极和所述第二电极的间隙的电极间间隙其中发生第一和第二电极之间的电阻值变化的现象，并且可以执行从预定的低电阻状态到预定的高电阻状态的转变以及从高电阻状态到低电阻状态时，在从高电阻状态向低电阻状态转变时，通过恒流电路将电流脉冲施加到存储元件。

2. 发明授权

US09130159B2 Method of fabricating element including nanogap electrodes 有权
标题翻译：制造纳米胶片电极元件的方法
公开(公告)号：US09130159B2
公开(公告)日：2015-09-08
申请号：US12756522
申请日：2010-04-08
申请人： Shigeo Furuta , Touru Sumiya , Yuichiro Masuda , Tsuyoshi Takahashi , Yutaka Hayashi , Masatoshi Ono
发明人： Shigeo Furuta , Touru Sumiya , Yuichiro Masuda , Tsuyoshi Takahashi , Yutaka Hayashi , Masatoshi Ono
IPC分类号： H01H11/00 , H01H65/00 , H01L45/00
CPC分类号： H01L45/1233 , H01L45/04 , H01L45/16 , Y10T29/49082 , Y10T29/49105
摘要： Disclosed is a fabrication method of an element with nanogap electrodes including a first electrode, a second electrode provided above the first electrode, and a gap provided between the first electrode and the second electrode, the gap being in an order of nanometer to allow resistive state to be switched by applying a predetermined voltage between the first electrode and the second electrode, the method comprising: forming the first electrode; forming a spacer on an upper surface of the first electrode; forming the second electrode in contact with an upper surface of the spacer; and removing the spacer to form the gap.
摘要翻译：公开了一种具有纳米隙电极的元件的制造方法，其包括第一电极，设置在第一电极上方的第二电极和设置在第一电极和第二电极之间的间隙，间隙为纳米级，以允许电阻状态通过在第一电极和第二电极之间施加预定电压进行切换，该方法包括：形成第一电极; 在所述第一电极的上表面上形成间隔物; 形成与间隔物的上表面接触的第二电极; 并移除间隔物以形成间隙。

3. 发明申请

US20130155757A1 Drive Method for Memory Element, and Storage Device Using Memory Element 有权
标题翻译：内存元素的驱动方法和使用内存元素的存储设备
公开(公告)号：US20130155757A1
公开(公告)日：2013-06-20
申请号：US13819217
申请日：2011-08-25
申请人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
发明人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
IPC分类号： G11C13/00
CPC分类号： G11C13/0002 , G11C13/003 , G11C13/0069 , G11C17/16 , G11C2013/009 , G11C2213/33 , G11C2213/52 , G11C2213/74 , G11C2213/79
摘要： A memory element includes an insulating substrate; a first electrode and a second electrode on the insulating substrate; and an inter-electrode gap portion that causes a change in resistance value between the first and second electrodes. Applied to the memory element from a pulse generating source is a first voltage pulse for shifting from a predetermined low-resistance state to a predetermined high-resistance state, and a second voltage pulse for shifting from the high-resistance state to the low-resistance state through a series-connected resistor, by which current flowing to the memory element after the change to a low resistance value is reduced. When shifting from the high to the low-resistance state, a voltage pulse is applied such that an electrical resistance between the pulse generating source and the memory element becomes higher than the electrical resistance shifting from the low to the high-resistance state.
摘要翻译：存储元件包括绝缘基板; 绝缘基板上的第一电极和第二电极; 以及引起第一和第二电极之间的电阻值变化的电极间间隙部分。从脉冲发生源施加到存储元件的是用于从预定的低电阻状态转换到预定的高电阻状态的第一电压脉冲和用于从高电阻状态转移到低电阻的第二电压脉冲通过串联电阻器的状态，通过该电阻减少在改变为低电阻值之后流向存储元件的电流。当从高电平状态转移到低电阻状态时，施加电压脉冲，使得脉冲发生源和存储元件之间的电阻变得高于从低电阻状态向高电阻状态的电阻移动。

4. 发明申请

US20130170285A1 Drive Method for Memory Element and Storage Device Using Memory Element 有权
标题翻译：使用内存元素的内存元素和存储设备的驱动方法
公开(公告)号：US20130170285A1
公开(公告)日：2013-07-04
申请号：US13819247
申请日：2011-08-25
申请人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
发明人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C2213/79 , H01L27/101
摘要： In a drive method for a memory element that includes an insulating substrate, a first electrode and a second electrode provided on the insulating substrate, and an inter-electrode gap portion provided between the first electrode and the second electrode and having a gap of the order of nanometers where a phenomenon of a change in resistance value between the first and second electrodes occurs, and that can perform a transition from a predetermined low-resistance state to a predetermined high-resistance state and a transition from the high-resistance state to the low-resistance state, a current pulse is applied to the memory element by a constant current circuit upon the transition from the high-resistance state to the low-resistance state.
摘要翻译：在包括绝缘基板的存储元件的驱动方法中，设置在所述绝缘基板上的第一电极和第二电极以及设置在所述第一电极和所述第二电极之间并且具有所述第一电极和所述第二电极的间隙的电极间间隙其中发生第一和第二电极之间的电阻值变化的现象，并且可以执行从预定的低电阻状态到预定的高电阻状态的转变以及从高电阻状态到低电阻状态时，在从高电阻状态向低电阻状态转变时，通过恒流电路将电流脉冲施加到存储元件。

5. 发明授权

US09135990B2 Drive method for memory element, and storage device using memory element 有权
标题翻译：存储器元件的驱动方法，以及使用存储元件的存储器件
公开(公告)号：US09135990B2
公开(公告)日：2015-09-15
申请号：US13819217
申请日：2011-08-25
申请人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
发明人： Tsuyoshi Takahashi , Yuichiro Masuda , Shigeo Furuta , Touru Sumiya , Masatoshi Ono , Yutaka Hayashi , Toshimi Fukuoka , Tetsuo Shimizu , Kumaragurubaran Somu , Hiroshi Suga , Yasuhisa Naitou
IPC分类号： G11C11/00 , G11C13/00 , G11C17/16
CPC分类号： G11C13/0002 , G11C13/003 , G11C13/0069 , G11C17/16 , G11C2013/009 , G11C2213/33 , G11C2213/52 , G11C2213/74 , G11C2213/79
摘要： A memory element includes an insulating substrate; a first electrode and a second electrode on the insulating substrate; and an inter-electrode gap portion that causes a change in resistance value between the first and second electrodes. Applied to the memory element from a pulse generating source is a first voltage pulse for shifting from a predetermined low-resistance state to a predetermined high-resistance state, and a second voltage pulse for shifting from the high-resistance state to the low-resistance state through a series-connected resistor, by which current flowing to the memory element after the change to a low resistance value is reduced. When shifting from the high to the low-resistance state, a voltage pulse is applied such that an electrical resistance between the pulse generating source and the memory element becomes higher than the electrical resistance shifting from the low to the high-resistance state.
摘要翻译：存储元件包括绝缘基板; 绝缘基板上的第一电极和第二电极; 以及引起第一和第二电极之间的电阻值变化的电极间间隙部分。从脉冲发生源施加到存储元件的是用于从预定的低电阻状态转换到预定的高电阻状态的第一电压脉冲和用于从高电阻状态转移到低电阻的第二电压脉冲通过串联电阻器的状态，通过该电阻减少在改变为低电阻值之后流向存储元件的电流。当从高电平状态转移到低电阻状态时，施加电压脉冲，使得脉冲发生源和存储元件之间的电阻变得高于从低电阻状态向高电阻状态的电阻移动。

6. 发明申请

US20100257726A1 Method of Fabricating Element Including Nanogap Electrodes 有权
标题翻译：包括纳米石墨电极的元件制造方法
公开(公告)号：US20100257726A1
公开(公告)日：2010-10-14
申请号：US12756522
申请日：2010-04-08
申请人： Shigeo FURUTA , Touru Sumiya , Yuichiro Masuda , Tsuyoshi Takahashi , Yutaka Hayashi , Masatoshi Ono
发明人： Shigeo FURUTA , Touru Sumiya , Yuichiro Masuda , Tsuyoshi Takahashi , Yutaka Hayashi , Masatoshi Ono
IPC分类号： H01C17/00
CPC分类号： H01L45/1233 , H01L45/04 , H01L45/16 , Y10T29/49082 , Y10T29/49105
摘要： Disclosed is a fabrication method of an element with nanogap electrodes including a first electrode, a second electrode provided above the first electrode, and a gap provided between the first electrode and the second electrode, the gap being in an order of nanometer to allow resistive state to be switched by applying a predetermined voltage between the first electrode and the second electrode, the method comprising: forming the first electrode; forming a spacer on an upper surface of the first electrode; forming the second electrode in contact with an upper surface of the spacer; and removing the spacer to form the gap.
摘要翻译：公开了一种具有纳米隙电极的元件的制造方法，其包括第一电极，设置在第一电极上方的第二电极和设置在第一电极和第二电极之间的间隙，间隙为纳米级，以允许电阻状态通过在第一电极和第二电极之间施加预定电压进行切换，该方法包括：形成第一电极; 在所述第一电极的上表面上形成间隔物; 形成与间隔物的上表面接触的第二电极; 并移除间隔物以形成间隙。

7. 发明授权

US08094484B2 Memory cell array 有权
标题翻译：存储单元阵列
公开(公告)号：US08094484B2
公开(公告)日：2012-01-10
申请号：US12644851
申请日：2009-12-22
申请人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
发明人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
IPC分类号： G11C11/00
CPC分类号： H01L27/24 , G11C13/00 , G11C13/0069 , G11C13/02 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.
摘要翻译：公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和门极阈值电压以下。

8. 发明申请

US20100165696A1 Memory Cell Array 有权
标题翻译：存储单元阵列
公开(公告)号：US20100165696A1
公开(公告)日：2010-07-01
申请号：US12644608
申请日：2009-12-22
申请人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
发明人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： H01L27/24 , G11C13/00 , G11C13/0069 , G11C13/02 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.
摘要翻译：公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线或更少。

9. 发明授权

US08174871B2 Memory cell array 有权
标题翻译：存储单元阵列
公开(公告)号：US08174871B2
公开(公告)日：2012-05-08
申请号：US12644608
申请日：2009-12-22
申请人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
发明人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
IPC分类号： G11C11/00
CPC分类号： H01L27/24 , G11C13/00 , G11C13/0069 , G11C13/02 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.
摘要翻译：公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线或更少。

10. 发明申请

US20100165695A1 Memory Cell Array 有权
标题翻译：存储单元阵列
公开(公告)号：US20100165695A1
公开(公告)日：2010-07-01
申请号：US12644851
申请日：2009-12-22
申请人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
发明人： Tsuyoshi Takahashi , Yutaka Hayashi , Yuichiro Masuda , Shigeo Furuta , Masatoshi Ono
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： H01L27/24 , G11C13/00 , G11C13/0069 , G11C13/02 , G11C2013/0071 , G11C2013/009 , G11C2213/79
摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.
摘要翻译：公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和门极阈值电压以下。

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