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1. 发明授权

US10816597B2 Single pin test interface for pin limited systems 有权
公开(公告)号：US10816597B2
公开(公告)日：2020-10-27
申请号：US15836363
申请日：2017-12-08
申请人： Silicon Laboratories Inc.
发明人： Huanhui Zhan , Krishna Pentakota , Stefan N. Mastovich
IPC分类号： G01R31/317 , G01R31/316
摘要： An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

2. 发明授权

US10812028B2 Power transfer device using an oscillator 有权
公开(公告)号：US10812028B2
公开(公告)日：2020-10-20
申请号：US16660027
申请日：2019-10-22
申请人： Silicon Laboratories Inc.
发明人： Mohammad Al-Shyoukh , Krishna Pentakota , Stefan N. Mastovich
IPC分类号： H03F3/217 , H02J50/05 , H02J50/80 , H02M3/335 , H02M5/458 , H02M7/797 , H02M1/08 , H01L29/66 , H02M3/338 , H02M1/34 , H02H9/00 , H03F3/04 , H01L29/78 , H02M1/00 , H02M1/32
摘要： A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

3. 发明申请

US20200052665A1 POWER TRANSFER DEVICE USING AN OSCILLATOR 审中-公开
公开(公告)号：US20200052665A1
公开(公告)日：2020-02-13
申请号：US16660027
申请日：2019-10-22
申请人： Silicon Laboratories Inc.
发明人： Mohammad Al-Shyoukh , Krishna Pentakota , Stefan N. Mastovich
IPC分类号： H03F3/217 , H01L29/66 , H02M1/08 , H02M7/797 , H02M5/458 , H02M3/335 , H02J50/80 , H02J50/05 , H02M3/338
摘要： A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

4. 发明申请

US20200099255A1 POWER RESONATOR WITH WIDE INPUT VOLTAGE RANGE FOR ISOLATED POWER TRANSFER 审中-公开
公开(公告)号：US20200099255A1
公开(公告)日：2020-03-26
申请号：US16141052
申请日：2018-09-25
申请人： Silicon Laboratories Inc.
发明人： Mohammad Al-Shyoukh , Krishna Pentakota , Stefan N. Mastovich
IPC分类号： H02J50/12 , H02M3/337 , H02M3/335 , H02M3/338
摘要： A power transfer device includes a first power supply node, a second power supply node, and an oscillator circuit configured to convert an input DC signal across the first power supply node and the second power supply node into an AC signal on a differential pair of nodes comprising a first node and a second node in response to a control signal. The oscillator circuit includes a regulated power supply node and an active shunt regulator circuit configured to clamp a peak voltage level across the regulated power supply node and the second power supply node to a clamped voltage level. The clamped voltage level is linearly related to a first voltage level on the first power supply node.

5. 发明授权

US10566930B2 Dynamically controlling a negative impedance of a voltage controlled oscillator 有权
公开(公告)号：US10566930B2
公开(公告)日：2020-02-18
申请号：US15498937
申请日：2017-04-27
申请人： Silicon Laboratories Inc.
发明人： Krishna Pentakota , Aslamali Rafi
IPC分类号： H03L5/00 , H03B5/12 , H03F3/19
摘要： In one embodiment, an apparatus includes a voltage controlled oscillator (VCO) to output an oscillating signal. The VCO may have a tank formed of at least one capacitor coupled in parallel with at least one inductor, and a plurality of transconductors to provide energy to the tank. At least one of the plurality of transconductors can be controllably switched to be coupled to the tank or to be decoupled from the tank.

6. 发明申请

US20150123714A1 HIGHLY LINEAR BUFFER 有权
标题翻译：高线性缓存器
公开(公告)号：US20150123714A1
公开(公告)日：2015-05-07
申请号：US14074241
申请日：2013-11-07
申请人： SILICON LABORATORIES INC.
发明人： Ruifeng Sun , Mustafa H. Koroglu , Ramin Khoini Poorfard , Yu Su , Krishna Pentakota , Pio Balmelli
IPC分类号： H03K17/16
CPC分类号： H03K17/16 , H03K2217/0063
摘要： Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.
摘要翻译：与缓冲电路有关的技术。在一个实施例中，电路包括配置为源极跟随器的第一晶体管和耦合到第一晶体管的栅极端子和第一晶体管的漏极端子的前馈通路。在该实施例中，前馈路径包括被配置为将前馈路径与输入信号的DC分量去耦到第一晶体管的栅极端子的电路。在该实施例中，电路被配置为基于输入信号来减小第一晶体管的漏 - 源电压。在一些实施例中，前馈路径包括配置为源极跟随器的第二晶体管，并且第二晶体管的源极端子耦合到第一晶体管的漏极端子。在各种实施例中，减小漏极 - 源极电压可以提高第一晶体管的线性。

7. 发明授权

US10326375B1 Isolated power transfer with integrated transformer and voltage control 有权
公开(公告)号：US10326375B1
公开(公告)日：2019-06-18
申请号：US15835234
申请日：2017-12-07
申请人： Silicon Laboratories Inc.
发明人： Krishna Pentakota , Mohammad Al-Shyoukh , Stefan N. Mastovich
IPC分类号： H04L7/00 , H02M3/335 , G01R19/18 , H01L21/48 , H01L23/498 , H01L23/66 , H03F3/213 , H03F3/195 , H02M7/537 , H01L23/64 , H01F19/08
摘要： An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.

8. 发明申请

US20190181764A1 ISOLATED POWER TRANSFER WITH INTEGRATED TRANSFORMER AND VOLTAGE CONTROL 审中-公开
公开(公告)号：US20190181764A1
公开(公告)日：2019-06-13
申请号：US15835234
申请日：2017-12-07
申请人： Silicon Laboratories Inc.
发明人： Krishna Pentakota , Mohammad Al-Shyoukh , Stefan N. Mastovich
IPC分类号： H02M3/335 , G01R19/18 , H01L21/48 , H01L23/498 , H01L23/64 , H01L23/66 , H03F3/213 , H03F3/195 , H02M7/537
摘要： An isolated power transfer device has a primary side and a secondary side isolated from the primary side by an isolation barrier. A secondary-side circuit includes a rectifier circuit coupled to a secondary-side conductive coil. The secondary-side circuit includes a first resistor coupled to a first power supply node and a terminal node. The secondary-side circuit includes a second resistor coupled to the terminal node and a second power supply node. The secondary-side circuit includes a first circuit to generate a feedback signal in response to a reference voltage and a signal on the terminal node. The feedback signal has a hysteretic band defined by the first resistor and the second resistor. The secondary-side circuit is configured as an AC/DC power converter that provides, on the first power supply node, an output DC signal having a voltage level based on a ratio of the first resistor to the second resistor.

9. 发明申请

US20190178937A1 SINGLE PIN TEST INTERFACE FOR PIN LIMITED SYSTEMS 审中-公开
公开(公告)号：US20190178937A1
公开(公告)日：2019-06-13
申请号：US15836363
申请日：2017-12-08
申请人： Silicon Laboratories Inc.
发明人： Huanhui Zhan , Krishna Pentakota , Stefan N. Mastovich
IPC分类号： G01R31/317 , G01R31/316
摘要： An integrated circuit includes a supply terminal to receive a supply voltage and a test terminal that operates in an input mode and an output mode. A test interface of the integrated circuit operates in a normal mode requiring a serial write to the test terminal to access test locations in the integrated circuit. The test interface also operates in an automatic mode in which addresses for test locations are auto incremented by toggling the supply voltage from a high voltage level to a low voltage level and back to the high voltage level. In an input mode, with the supply voltage at the low voltage level, the test pin receives configuration and address information. In output mode, with the supply voltage at the high voltage level, the test pin supplies test information corresponding to the address information received.

10. 发明授权

US10033421B2 Multi-standard, multi-channel expandable TV/satellite receiver 有权
公开(公告)号：US10033421B2
公开(公告)日：2018-07-24
申请号：US15168318
申请日：2016-05-31
申请人： Silicon Laboratories Inc.
发明人： Vitor Pereira , Mustafa Koroglu , Ruifeng Sun , Ramin Khoini-Poorfard , Abdulkerim Coban , Yu Su , Krishna Pentakota
IPC分类号： H04B1/30 , H04B1/00 , H04B1/10
摘要： In one example, a semiconductor die includes multi-standard, multi-channel expandable television/satellite receiver that can be flexibly implemented in a number of different configurations to enable incorporation into a plurality of different systems. The semiconductor die may include multiple tuners to receive and tune a terrestrial radio frequency (RF) signal and a satellite RF signal. These tuners may include different frequency synthesizers including voltage controlled oscillators (VCOs) to generate VCO signals at different frequencies, mixers to downconvert the RF signals to baseband signals using the VCO signals. In an implementation, the semiconductor die may further include shared circuitry coupled to the tuners to digitize, process and demodulate the baseband signals.

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