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1. 发明申请

US20120030533A1 IMPLEMENTING SWITCHING FACTOR REDUCTION IN LBIST 失效
标题翻译：实施LBIT中的切换因子减少
公开(公告)号：US20120030533A1
公开(公告)日：2012-02-02
申请号：US12844120
申请日：2010-07-27
申请人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
发明人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318385 , G06F11/27
摘要： A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.
摘要翻译：提供了一种用于实现逻辑内置自检（LBIST）诊断中的开关因数降低的方法和电路，以及主题电路所在的设计结构。开关因子降低逻辑耦合到伪随机模式发生器（PRPG），该模拟生成器将信道输入模式提供给用于LBIST诊断的多个LBIST信道。开关因子降低逻辑选择性地为多个通道中的每个通道提供受控通道输入模式。

2. 发明授权

US08407542B2 Implementing switching factor reduction in LBIST 失效
标题翻译：实现LBIST中的开关因数降低
公开(公告)号：US08407542B2
公开(公告)日：2013-03-26
申请号：US12844120
申请日：2010-07-27
申请人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
发明人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
IPC分类号： G06F11/00
CPC分类号： G01R31/318385 , G06F11/27
摘要： A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.
摘要翻译：提供了一种用于实现逻辑内置自检（LBIST）诊断中的开关因数降低的方法和电路，以及主题电路所在的设计结构。开关因子降低逻辑耦合到伪随机模式发生器（PRPG），该模拟生成器将信道输入模式提供给用于LBIST诊断的多个LBIST信道。开关因子降低逻辑选择性地为多个通道中的每个通道提供受控通道输入模式。

3. 发明申请

US20120159273A1 Dynamic Scan 失效
标题翻译：动态扫描
公开(公告)号：US20120159273A1
公开(公告)日：2012-06-21
申请号：US12968627
申请日：2010-12-15
申请人： Steven M. Douskey , Ryan Andrew Fitch , Michael J. Hamilton , Amanda R. Kaufer
发明人： Steven M. Douskey , Ryan Andrew Fitch , Michael J. Hamilton , Amanda R. Kaufer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318558
摘要： In a test data access system, a shift register is coupled the test data in pin. A first multiplexer is in data communication with the TDI pin and is configured to receive data from the TDI pin and to transmit data to each of the instruments. The first multiplexer is also configured to receive data from a data recirculation bit and to transmit data from the TDI pin to a plurality of instruments when the recirculation bit has a first value and to transmit data to the plurality of instruments from a recirculation line when the recirculation bit has a second value, different from the first value. A second multiplexer is configured to receive data from each of the plurality of instruments and is configured to transmit data from a selected one of the plurality of instruments, selected based on a value of data in the shift register. A first AND gate is configured to generate a gates clock to the shift register. A second AND gate is responsive to the first AND gate, configured to lock the shift register. A third AND gate, responsive to the first AND gate, is configured to control clocking to the plurality of instruments.
摘要翻译：在测试数据访问系统中，移位寄存器以引脚方式耦合测试数据。第一个多路复用器与TDI引脚进行数据通信，并配置为从TDI引脚接收数据并向每个仪器传输数据。第一多路复用器还被配置为从数据再循环位接收数据，并且当再循环位具有第一值时将数据从TDI引脚传输到多个仪器，并且当第二复用器当再循环线时将数据从再循环管线传送到多个仪器再循环位具有与第一值不同的第二值。第二多路复用器被配置为从所述多个仪器中的每一个接收数据，并且被配置为基于所述移位寄存器中的数据值来选择所选择的所述多个仪器中的数据。第一与门被配置为向移位寄存器产生门时钟。第二与门响应于第一与门，被配置为锁定移位寄存器。响应于第一与门的第三与门配置成控制对多个仪器的时钟。

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