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1. 发明申请

US20120030533A1 IMPLEMENTING SWITCHING FACTOR REDUCTION IN LBIST 失效
标题翻译：实施LBIT中的切换因子减少
公开(公告)号：US20120030533A1
公开(公告)日：2012-02-02
申请号：US12844120
申请日：2010-07-27
申请人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
发明人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318385 , G06F11/27
摘要： A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.
摘要翻译：提供了一种用于实现逻辑内置自检（LBIST）诊断中的开关因数降低的方法和电路，以及主题电路所在的设计结构。开关因子降低逻辑耦合到伪随机模式发生器（PRPG），该模拟生成器将信道输入模式提供给用于LBIST诊断的多个LBIST信道。开关因子降低逻辑选择性地为多个通道中的每个通道提供受控通道输入模式。

2. 发明授权

US08407542B2 Implementing switching factor reduction in LBIST 失效
标题翻译：实现LBIST中的开关因数降低
公开(公告)号：US08407542B2
公开(公告)日：2013-03-26
申请号：US12844120
申请日：2010-07-27
申请人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
发明人： Steven Michael Douskey , Ryan Andrew Fitch , Michael John Hamilton , Amanda Renee Kaufer
IPC分类号： G06F11/00
CPC分类号： G01R31/318385 , G06F11/27
摘要： A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.
摘要翻译：提供了一种用于实现逻辑内置自检（LBIST）诊断中的开关因数降低的方法和电路，以及主题电路所在的设计结构。开关因子降低逻辑耦合到伪随机模式发生器（PRPG），该模拟生成器将信道输入模式提供给用于LBIST诊断的多个LBIST信道。开关因子降低逻辑选择性地为多个通道中的每个通道提供受控通道输入模式。

3. 发明申请

US20100023820A1 Asynchronous Communication Apparatus Using JTAG Test Data Registers 失效
标题翻译：使用JTAG测试数据寄存器的异步通信设备
公开(公告)号：US20100023820A1
公开(公告)日：2010-01-28
申请号：US12178776
申请日：2008-07-24
申请人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
发明人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318558
摘要： An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.
摘要翻译：由IEEE 1149.1联合标签动作组（JTAG）接口标准定义的测试数据寄存器（TDR）结构的调整，以提供调试路径。现有的多核处理器解决方案已被覆盖，但是提供了一个更通用的解决方案的扩展。通常，本装置用于扩展IEEE 1149.1 JTAG标准以提供用于旁路测试电路和与功能电路双向通信的异步协议。该装置包括具有功能寄存器和JTAG标准TDR的集成电路。数字逻辑被配置为控制JTAG标准TDR和功能寄存器之间的数据直接传输。

4. 发明授权

US07949918B2 Asynchronous communication using standard boundary architecture cells 失效
标题翻译：使用标准边界架构单元的异步通信
公开(公告)号：US07949918B2
公开(公告)日：2011-05-24
申请号：US12178833
申请日：2008-07-24
申请人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
发明人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318558
摘要： An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR. Further still, a digital logic interface is configured to control the direct transfer of data between the JTAG standard parallel TDR and a corresponding one of the plurality of function registers. As a result of the re-use of existing boundary scan architecture, a significant reduction in wiring congestion is realized. Thus, asynchronous communication is provided without sacrificing valuable integrated circuit real estate.
摘要翻译：由IEEE 1149.1联合测试动作组（JTAG）接口标准定义的标准边界单元架构的适配，以通过重新使用JTAG标准测试数据寄存器（TDR）和接口为功能电路提供路径。现有的多核处理器解决方案已被覆盖，但是提供了一个更通用的解决方案的扩展。通常，集成电路具有多个功能寄存器以及多个I / O单元。 I / O单元布置在位于集成电路功能电路边界周围的串行通信链路中。每个I / O单元包括与相邻I / O单元串行通信的JTAG标准串行TDR。此外，每个I / O单元都包括与I / O单元的JTAG标准串行TDR相关联并与之并联的JTAG标准并行TDR。此外，数字逻辑接口被配置为控制在JTAG标准并行TDR和多个功能寄存器中的相应一个之间的数据的直接传送。由于重新利用现有的边界扫描架构，实现了布线拥塞的显着降低。因此，提供异步通信而不牺牲有价值的集成电路的不动产。

5. 发明授权

US07114109B2 Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features 失效
标题翻译：用于定制和监控多个接口并实现增强的容错和隔离功能的方法和设备
公开(公告)号：US07114109B2
公开(公告)日：2006-09-26
申请号：US10798912
申请日：2004-03-11
申请人： James Fred Daily , Steven Michael Douskey , Michael John Hamilton
发明人： James Fred Daily , Steven Michael Douskey , Michael John Hamilton
IPC分类号： G01R31/28
CPC分类号： G01R31/318563
摘要： A method and apparatus are provided for customizing and monitoring multiple interfaces, such as, multiple IEEE 1149.1 standard joint test access group (JTAG) interfaces and implementing enhanced fault tolerance and isolation features. A first interface is connected to a pair of master sources. A second interface is connected to a plurality of target interfaces; and a third interface is provided for a plurality of predefined control signals. A pair of redundant selectors is provided for coupling a select signal to the first multiplexer for selecting one of the plurality of target interfaces. A pair of redundant ATTENTION monitor functions is provided for monitoring ATTENTION signals for each of the plurality of target interfaces.
摘要翻译：提供了一种方法和装置，用于定制和监视多个接口，例如多个IEEE 1149.1标准联合测试接入组（JTAG）接口，并实现增强的容错和隔离特性。第一个接口连接到一对主源。第二接口连接到多个目标接口; 并且为多个预定义的控制信号提供第三接口。提供一对冗余选择器，用于将选择信号耦合到第一多路复用器，用于选择多个目标接口之一。提供了一对冗余注意监视功能，用于监视多个目标接口中的每一个的“注意”信号。

6. 发明授权

US07890824B2 Asynchronous communication apparatus using JTAG test data registers 失效
标题翻译：使用JTAG测试数据寄存器的异步通信装置
公开(公告)号：US07890824B2
公开(公告)日：2011-02-15
申请号：US12178776
申请日：2008-07-24
申请人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
发明人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
IPC分类号： G01R31/28
CPC分类号： G01R31/318558
摘要： An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.
摘要翻译：由IEEE 1149.1联合标签动作组（JTAG）接口标准定义的测试数据寄存器（TDR）结构的调整，以提供调试路径。现有的多核处理器解决方案已被覆盖，但是提供了一个更通用的解决方案的扩展。通常，本装置用于扩展IEEE 1149.1 JTAG标准以提供用于旁路测试电路和与功能电路双向通信的异步协议。该装置包括具有功能寄存器和JTAG标准TDR的集成电路。数字逻辑被配置为控制JTAG标准TDR和功能寄存器之间的数据直接传输。

7. 发明申请

US20100023821A1 Asynchronous Communication Using Standard Boundary Architecture Cells 失效
标题翻译：使用标准边界结构单元的异步通信
公开(公告)号：US20100023821A1
公开(公告)日：2010-01-28
申请号：US12178833
申请日：2008-07-24
申请人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
发明人： Steven Michael Douskey , Michael John Hamilton , Brandon Edward Schenck
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318594 , G01R31/318558
摘要： An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR. Further still, a digital logic interface is configured to control the direct transfer of data between the JTAG standard parallel TDR and a corresponding one of the plurality of function registers. As a result of the re-use of existing boundary scan architecture, a significant reduction in wiring congestion is realized. Thus, asynchronous communication is provided without sacrificing valuable integrated circuit real estate.
摘要翻译：由IEEE 1149.1联合测试动作组（JTAG）接口标准定义的标准边界单元架构的适配，以通过重新使用JTAG标准测试数据寄存器（TDR）和接口为功能电路提供路径。现有的多核处理器解决方案已被覆盖，但是提供了一个更通用的解决方案的扩展。通常，集成电路具有多个功能寄存器以及多个I / O单元。 I / O单元布置在位于集成电路功能电路边界周围的串行通信链路中。每个I / O单元包括与相邻I / O单元串行通信的JTAG标准串行TDR。此外，每个I / O单元都包括与I / O单元的JTAG标准串行TDR相关联并与之并联的JTAG标准并行TDR。此外，数字逻辑接口被配置为控制在JTAG标准并行TDR和多个功能寄存器中的相应一个之间的数据的直接传送。由于重新利用现有的边界扫描架构，实现了布线拥塞的显着降低。因此，提供异步通信而不牺牲有价值的集成电路的不动产。

8. 发明授权

US06807645B2 Method and apparatus for implementing enhanced LBIST diagnostics of intermittent failures 失效
标题翻译：用于实施增强的LBIST诊断间歇性故障的方法和装置
公开(公告)号：US06807645B2
公开(公告)日：2004-10-19
申请号：US10066825
申请日：2002-02-04
申请人： Frank William Angelotti , Steven Michael Douskey
发明人： Frank William Angelotti , Steven Michael Douskey
IPC分类号： G01R3128
CPC分类号： G01R31/31813
摘要： A method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics. First multiplexers are respectively coupled between adjacent sequential channels of a plurality of sequential channels under test. Each of the first multiplexers selectively receives a first data input in a first scan mode with the sequential channels configured in a common scan path and a second data input in a second scan mode with each the sequential channels configured in a separate scan path responsive to a first control signal. A first multiple input signature register (MISR) including multiple MISR inputs is coupled to a respective one of the plurality of sequential channels under test. A blocker function is configured for blocking all MISR inputs except for a single MISR input receiving the test data output of the last sequential channel responsive to a recirculate control signal. A second MISR shadow register is coupled to the first multiple input signature register.
摘要翻译：提供了一种用于增强逻辑内置自检（LBIST）诊断的方法和装置。第一多路复用器分别耦合在被测试的多个顺序通道的相邻顺序通道之间。每个第一多路复用器以第一扫描模式选择性地接收第一数据输入，其中顺序通道被配置在公共扫描路径中，而第二数据输入以第二扫描模式输入，每个顺序通道被配置在单独的扫描路径中，第一控制信号。包括多个MISR输入的第一多输入签名寄存器（MISR）被耦合到被测试的多个顺序通道中的相应一个。阻塞器功能被配置为阻止所有MISR输入，除了响应于再循环控制信号接收最后顺序通道的测试数据输出的单个MISR输入。第二MISR影子寄存器耦合到第一多输入签名寄存器。

9. 发明授权

US06735543B2 Method and apparatus for testing, characterizing and tuning a chip interface 失效
标题翻译：用于测试，表征和调整芯片接口的方法和装置
公开(公告)号：US06735543B2
公开(公告)日：2004-05-11
申请号：US09996839
申请日：2001-11-29
申请人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
发明人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
IPC分类号： G06F1900
CPC分类号： G01R31/31813 , G01R31/318385
摘要： An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.
摘要翻译：传输芯片中的芯片间线路传输电路和接收芯片中的互补接收电路通过在两个芯片上分别产生相同的伪随机测试数据，比较数据和记录错误，提供表征芯片间接口的能力。优选地，可以在单独的线路基础上调整一个或两个芯片以通过改变阈值检测电压，信号延迟和/或驱动器功率来减少误差。接收机电路优选地包含用于对测试周期和错误进行计数的计数器，其可以针对任何特定线路或类型的错误被屏蔽。因此，根据优选实施例的可调谐和可表征的接口因此支持针对各种调谐参数设置在各个线路上准确地确定低错误率。

10. 发明申请

US20080172643A1 High-Speed Leaf Clock Frequency-Divider/Splitter 审中-公开
标题翻译：高速叶片时钟分频器/分路器
公开(公告)号：US20080172643A1
公开(公告)日：2008-07-17
申请号：US11859175
申请日：2007-09-21
申请人： Steven Michael Douskey , Matthew Roger Ellavsky
发明人： Steven Michael Douskey , Matthew Roger Ellavsky
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F1/10 , G06F2217/62
摘要： A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. In one embodiment, the novel clock splitter is incorporated into a design structure that is embodied in a machine readable medium used for designing, manufacturing, or testing a design of the novel clock splitter.
摘要翻译：提出了一种具有本地内部时钟分频器的新型时钟分离器。时钟分配器包括振荡器时钟分离器，其中振荡器时钟分配器将振荡器时钟信号分离成B时钟和C时钟; 时钟分频器，其中时钟分频器选择性地抑制C时钟中的时钟脉冲以产生比振荡器时钟慢的C速时钟信号; 和B / C时钟顺序逻辑，其中B / C时钟顺序逻辑相位相对于B时钟移位C时钟。时钟分频器可以选择性地抑制B时钟脉冲以产生较慢的B时钟信号。在一个实施例中，新颖的时钟分离器被并入设计结构中，体现在用于设计，制造或测试新型时钟分离器的设计的机器可读介质中。

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