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1. 发明授权

US07843761B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07843761B2
公开(公告)日：2010-11-30
申请号：US12136513
申请日：2008-06-10
申请人： Sun-Suk Yang , Yong-Ki Kim
发明人： Sun-Suk Yang , Yong-Ki Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.
摘要翻译：半导体存储器件能够确保用于接收地址的建立/保持时间的余量。该装置包括地址缓冲单元，数据输入/输出线，选择单元和输出电路。地址缓冲单元缓冲输入地址。数据输入/输出线用单元阵列传输数据。选择单元根据设备的模式选择性地输出从地址缓冲单元传送的缓冲地址和通过数据输入/输出线传输的数据。输出电路锁存要从设备输出的选择单元的输出。

2. 发明申请

US20090086564A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090086564A1
公开(公告)日：2009-04-02
申请号：US12136513
申请日：2008-06-10
申请人： Sun-Suk YANG , Yong-Ki Kim
发明人： Sun-Suk YANG , Yong-Ki Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.
摘要翻译：半导体存储器件能够确保用于接收地址的建立/保持时间的余量。该装置包括地址缓冲单元，数据输入/输出线，选择单元和输出电路。地址缓冲单元缓冲输入地址。数据输入/输出线用单元阵列传输数据。选择单元根据设备的模式选择性地输出从地址缓冲单元传送的缓冲地址和通过数据输入/输出线传输的数据。输出电路锁存要从设备输出的选择单元的输出。

3. 发明授权

US08284880B2 Clock data recovery circuit and method for operating the same 失效
标题翻译：时钟数据恢复电路及其操作方法
公开(公告)号：US08284880B2
公开(公告)日：2012-10-09
申请号：US12005850
申请日：2007-12-28
申请人： Kyung-Hoon Kim , Jong-Ho Kang , Yong-Ki Kim , Dae-Han Kwon , Sang-Yeon Byeon
发明人： Kyung-Hoon Kim , Jong-Ho Kang , Yong-Ki Kim , Dae-Han Kwon , Sang-Yeon Byeon
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , G11C7/222 , H03L7/089 , H03L7/091 , H03L7/093
摘要： A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.
摘要翻译：时钟数据恢复（CDR）电路占据了高集成度半导体器件，电子器件和系统所需的较小面积，并且易于进行设计修改。 CDR电路包括：数字滤波器，被配置为滤波在预定周期期间接收到的相位比较结果信号和输出控制信号;驱动器，被配置为通过调整预定周期来控制数字滤波器;以及输入/输出电路，被配置为识别输入和输出的数据和时钟响应于控制信号。

4. 发明授权

US07701790B2 Semiconductor memory device including reset control circuit 失效
标题翻译：半导体存储器件包括复位控制电路
公开(公告)号：US07701790B2
公开(公告)日：2010-04-20
申请号：US11528642
申请日：2006-09-28
申请人： Chang-Ho Do , Yong-Ki Kim
发明人： Chang-Ho Do , Yong-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/12 , G11C11/406 , G11C11/4072 , G11C11/4094
摘要： A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.
摘要翻译：一种在系统中使用的半导体存储器件包括：复位信号发生器，用于响应于系统的复位操作的开始定时和终止定时，分别产生复位输入信号和复位输出信号; 以及复位控制器，用于响应于复位输入信号和响应于复位退出信号的刷新操作执行预充电操作。

5. 发明授权

US07977968B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07977968B2
公开(公告)日：2011-07-12
申请号：US12288882
申请日：2008-10-24
申请人： Yong-Ki Kim , Kyung-Hoon Kim
发明人： Yong-Ki Kim , Kyung-Hoon Kim
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1048 , G11C11/4093
摘要： A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.
摘要翻译：一种半导体存储器件，包括：用于基于从外部源输入的代码控制信号输出多个代码信号的代码通道; 用于解码芯片选择信号的终端电阻器解码器，芯片终端（ODT）控制信号和多个代码信号，并且基于解码的信号输出多个选择信号; 以及ODT块，用于为输出数据焊盘提供响应于所述多个选择信号而选择的终端电阻器的阻抗。

6. 发明授权

US07821812B2 Low-power DRAM and method for driving the same 有权
标题翻译：低功耗DRAM及其驱动方法
公开(公告)号：US07821812B2
公开(公告)日：2010-10-26
申请号：US11976241
申请日：2007-10-23
申请人： Yong-Ki Kim
发明人： Yong-Ki Kim
IPC分类号： G11C11/24
CPC分类号： G11C8/08 , G11C5/025 , G11C11/4082 , G11C11/4087 , G11C2207/2245
摘要： A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured to decode a part of most significant bits (MSB) of the column address to locally enable a part of one page area corresponding to the row address; and a column decoder configured to decode the column address.
摘要翻译：动态随机存取存储器包括：地址锁存器，被配置为响应于行地址选通（RAS）信号来锁存行地址并响应于列地址选通（CAS）信号锁存列地址; 配置为解码行地址的行解码器; 启动器，被配置为对列地址的最高有效位（MSB）的一部分进行解码，以本地启用对应于行地址的一个页区域的一部分; 以及列解码器，其被配置为对列地址进行解码。

7. 发明申请

US20100149891A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING RESET CONTROL CIRCUIT 失效
标题翻译：包括复位控制电路的半导体存储器件
公开(公告)号：US20100149891A1
公开(公告)日：2010-06-17
申请号：US12715146
申请日：2010-03-01
申请人： Chang-Ho Do , Yong-Ki Kim
发明人： Chang-Ho Do , Yong-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/12 , G11C11/406 , G11C11/4072 , G11C11/4094
摘要： A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.
摘要翻译：一种在系统中使用的半导体存储器件包括：复位信号发生器，用于响应于系统的复位操作的开始定时和终止定时，分别产生复位输入信号和复位输出信号; 以及复位控制器，用于响应于复位输入信号和响应于复位退出信号的刷新操作执行预充电操作。

8. 发明申请

US20090116601A1 Clock data recovery circuit and method for operating the same 失效
标题翻译：时钟数据恢复电路及其操作方法
公开(公告)号：US20090116601A1
公开(公告)日：2009-05-07
申请号：US12005850
申请日：2007-12-28
申请人： Kyung-Hoon Kim , Jong-Ho Kang , Yong-Ki Kim , Dae-Han Kwon , Sang-Yeon Byeon
发明人： Kyung-Hoon Kim , Jong-Ho Kang , Yong-Ki Kim , Dae-Han Kwon , Sang-Yeon Byeon
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , G11C7/222 , H03L7/089 , H03L7/091 , H03L7/093
摘要： A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals.
摘要翻译：时钟数据恢复（CDR）电路占据了高集成度半导体器件，电子器件和系统所需的较小面积，并且易于进行设计修改。 CDR电路包括：数字滤波器，被配置为滤波在预定周期期间接收到的相位比较结果信号和输出控制信号;驱动器，被配置为通过调整预定周期来控制数字滤波器;以及输入/输出电路，被配置为识别输入和输出的数据和时钟响应于控制信号。

9. 发明授权

US06459307B2 Input buffer having dual paths 有权
公开(公告)号：US06459307B2
公开(公告)日：2002-10-01
申请号：US09896437
申请日：2001-06-28
申请人： Yong-Ki Kim
发明人： Yong-Ki Kim
IPC分类号： H03K300
CPC分类号： H03K19/01707
摘要： An input buffer of the present invention has dual paths for increasing input signal processing speed by using two input buffers having input characteristics that differ from each other. The input buffer includes an input terminal receiving an external input signal; and first and second input buffers, both coupled to the input terminal for transferring an external input signal. The output signal of the second input buffer is blocked when the first input buffer transfers the external input signal, and the output signal of the first input buffer is blocked when the second input buffer transfers the external input signal.

10. 发明授权

US07986581B2 Semiconductor memory device including reset control circuit 失效
标题翻译：半导体存储器件包括复位控制电路
公开(公告)号：US07986581B2
公开(公告)日：2011-07-26
申请号：US12715146
申请日：2010-03-01
申请人： Chang-Ho Do , Yong-Ki Kim
发明人： Chang-Ho Do , Yong-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/20 , G11C7/12 , G11C11/406 , G11C11/4072 , G11C11/4094
摘要： A semiconductor memory device for use in a system includes a reset signal generator for generating a reset entry signal and a reset exit signal respectively in response to a start timing and a termination timing of a reset operation of the system; and a reset controller for performing a precharge operation in response to the reset entry signal and a refresh operation in response to the reset exit signal.
摘要翻译：一种在系统中使用的半导体存储器件包括：复位信号发生器，用于响应于系统的复位操作的开始定时和终止定时，分别产生复位输入信号和复位输出信号; 以及复位控制器，用于响应于复位输入信号和响应于复位退出信号的刷新操作执行预充电操作。

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