专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07631241B2 Apparatus and method for decoding low density parity check codes 有权
标题翻译：解码低密度奇偶校验码的装置和方法
公开(公告)号：US07631241B2
公开(公告)日：2009-12-08
申请号：US11133287
申请日：2005-05-20
申请人： Sung-Jin Park , Min-Goo Kim , Nam Yul Yu , Han-Ju Kim
发明人： Sung-Jin Park , Min-Goo Kim , Nam Yul Yu , Han-Ju Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/6566 , H03M13/1137
摘要： An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.
摘要翻译：提供了一种用于解码低密度奇偶校验（LDPC）码的装置和方法。由多个单元存储器构成的存储器模块存储可靠性值。可变节点处理器执行与变量节点相关联的计算，并且分别在列方向上更新存储器模块的数据。检查节点处理器执行与校验节点相关联的计算，并分别更新存储器模块在行方向上的数据。奇偶校验器确定所有错误是否已经被校正，使得执行迭代解码过程。存储器访问控制模块选择要由可变节点处理器或校验节点处理器更新的单元存储器。

2. 发明申请

US20060107193A1 Method and apparatus for efficiently decoding low density parity check code 审中-公开
标题翻译：用于有效解码低密度奇偶校验码的方法和装置
公开(公告)号：US20060107193A1
公开(公告)日：2006-05-18
申请号：US11247188
申请日：2005-10-12
申请人： Sung-Jin Park , Sang-Hyo Kim , Han-Ju Kim , Min-Goo Kim
发明人： Sung-Jin Park , Sang-Hyo Kim , Han-Ju Kim , Min-Goo Kim
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/1145 , H03M13/1105 , H03M13/1111 , H03M13/1134 , H03M13/1137
摘要： A method and apparatus are provided for decoding a forward error correction code in a mobile communication system using a LDPC code. A check node processor performs check node processing on information received with a plurality of check nodes and an accumulator accumulates check node output values from the check node processor with previous accumulated values. An edge memory stores the check node output values, and two accumulation memories separately store accumulated values from the accumulator and the previous accumulated values. A subtractor subtracts the check node output values from the accumulated values, and a hard-decision block performs hard-decision on the received information and the output value of the subtractor. A bit buffer stores the hard-decision result, and a parity check block performs parity check on the hard-decision result to determine whether to stop iterative decoding. A multiplexer delivers the subtraction result values to both the check node processor and the hard-decision block.
摘要翻译：提供一种用于使用LDPC码对移动通信系统中的前向纠错码进行解码的方法和装置。校验节点处理器对由多个校验节点接收的信息执行校验节点处理，并且累加器从具有先前累积值的校验节点处理器累加校验节点输出值。边缘存储器存储校验节点输出值，并且两个累积存储器分别存储来自累加器的累加值和先前累积值。减法器从累加值中减去校验节点输出值，硬判决块对接收到的信息和减法器的输出值进行硬判决。位缓冲器存储硬判决结果，奇偶校验块对硬判决结果执行奇偶校验，以确定是否停止迭代解码。多路复用器将减法结果值递送给校验节点处理器和硬判决块。

3. 发明授权

US07454685B2 Method and apparatus for decoding low density parity check code using united node processing 有权
标题翻译：使用联合节点处理解码低密度奇偶校验码的方法和装置
公开(公告)号：US07454685B2
公开(公告)日：2008-11-18
申请号：US11283732
申请日：2005-11-22
申请人： Sang-Hyo Kim , Sung-Jin Park , Han-Ju Kim , Min-Goo Kim
发明人： Sang-Hyo Kim , Sung-Jin Park , Han-Ju Kim , Min-Goo Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/1137 , H03M13/1114 , H03M13/114 , H03M13/116
摘要： A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.
摘要翻译：提供了一种解码包括多个校验节点和多个可变节点的LDPC码的方法和装置。该装置包括校验节点选择调度器，该校验节点选择调度器选择校验节点中的至少一个，将可变节点的输入LLR值存储为初始LLR值的LLR存储器，并且存储用于连接到所选校验节点的变量节点的更新的LLR值以及检查节点消息存储器，其将选择的校验节点上指示校验节点处理的结果值的校验节点消息存储。该装置还包括至少一个联合节点处理器，其通过从从LLR存储器读取的相应LLR值中减去所选择的校验节点的校验节点消息来生成变量节点消息，对变量节点消息执行校验节点处理，计算LLR 通过将变量节点消息添加到校验节点处理结果值来更新值，并将计算出的LLR值传递给LLR存储器。

4. 发明申请

US20060123318A1 Method and apparatus for decoding low density parity check code using united node processing 有权
标题翻译：使用联合节点处理解码低密度奇偶校验码的方法和装置
公开(公告)号：US20060123318A1
公开(公告)日：2006-06-08
申请号：US11283732
申请日：2005-11-22
申请人： Sang-Hyo Kim , Sung-Jin Park , Han-Ju Kim , Min-Goo Kim
发明人： Sang-Hyo Kim , Sung-Jin Park , Han-Ju Kim , Min-Goo Kim
IPC分类号： H03M13/00
CPC分类号： H03M13/1137 , H03M13/1114 , H03M13/114 , H03M13/116
摘要： A method and apparatus are provided for decoding an LDPC code including a plurality of check nodes and a plurality of variable nodes. The apparatus includes a check node selection scheduler that selects at least one of the check nodes, an LLR memory that stores an input LLR value for the variable nodes as an initial LLR value and stores updated LLR values for variable nodes connected to the selected check node, and a check node message memory that stores a check node message indicating a result value of check node processing on the selected check node. The apparatus further includes at least one united node processor that generates a variable node message by subtracting the check node message of the selected check node from corresponding LLR values read from the LLR memory, performs check node processing on the variable node message, calculates an LLR value updated by adding the variable node message to the check node processing result value, and delivers the calculated LLR value to the LLR memory.
摘要翻译：提供了一种解码包括多个校验节点和多个可变节点的LDPC码的方法和装置。该装置包括校验节点选择调度器，该校验节点选择调度器选择校验节点中的至少一个，将可变节点的输入LLR值存储为初始LLR值的LLR存储器，并且存储用于连接到所选校验节点的变量节点的更新的LLR值以及检查节点消息存储器，其将选择的校验节点上指示校验节点处理的结果值的校验节点消息存储。该装置还包括至少一个联合节点处理器，其通过从从LLR存储器读取的相应LLR值中减去所选择的校验节点的校验节点消息来生成变量节点消息，对变量节点消息执行校验节点处理，计算LLR 通过将变量节点消息添加到校验节点处理结果值来更新值，并将计算出的LLR值传递给LLR存储器。

5. 发明申请

US20050262420A1 Apparatus and method for decoding low density parity check codes 有权
标题翻译：解码低密度奇偶校验码的装置和方法
公开(公告)号：US20050262420A1
公开(公告)日：2005-11-24
申请号：US11133287
申请日：2005-05-20
申请人： Sung-Jin Park , Min-Goo Kim , Nam Yu , Han-Ju Kim
发明人： Sung-Jin Park , Min-Goo Kim , Nam Yu , Han-Ju Kim
IPC分类号： H04L27/18 , H03M13/00 , H03M13/11
CPC分类号： H03M13/6566 , H03M13/1137
摘要： An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.
摘要翻译：提供了一种用于解码低密度奇偶校验（LDPC）码的装置和方法。由多个单元存储器构成的存储器模块存储可靠性值。可变节点处理器执行与变量节点相关联的计算，并且分别在列方向上更新存储器模块的数据。检查节点处理器执行与校验节点相关联的计算，并分别更新存储器模块在行方向上的数据。奇偶校验器确定所有错误是否已经被校正，使得执行迭代解码过程。存储器访问控制模块选择要由可变节点处理器或校验节点处理器更新的单元存储器。

6. 发明申请

US20070130495A1 Apparatus and method of multi-cyclic redundancy checking for section detection and reliability information acquisition in a DVB-H system 审中-公开
标题翻译： DVB-H系统中的段检测和可靠性信息采集的多循环冗余校验装置和方法
公开(公告)号：US20070130495A1
公开(公告)日：2007-06-07
申请号：US11523323
申请日：2006-09-18
申请人： Jung-Wook Yoon , Ji-Won Ha , Min-Goo Kim , Sung-Jin Park
发明人： Jung-Wook Yoon , Ji-Won Ha , Min-Goo Kim , Sung-Jin Park
IPC分类号： H03M13/00
CPC分类号： H04L1/0061 , H04L1/0046 , H04L1/0072
摘要： A method and apparatus of multi-Cyclic Redundancy Checking (CRC) are provided for section detection and reliability information acquisition in a Digital Video Broadcasting-Handheld (DVB-H) system. A Packet Identifier (PID) filtering process is performed for a packet received through a radio network. A transport stream packet including section data is detected. A CRC process is performed for a payload of an associated section using header information of the section data and frame buffering is processed. The method and apparatus can perform CRC in a parallel fashion using multiple CRC checkers without interference between adjacent sections and can perform section detection and reliability verification.
摘要翻译：提供了一种多循环冗余校验（CRC）方法和装置，用于数字视频广播手持（DVB-H）系统中的区段检测和可靠性信息采集。对通过无线电网络接收的分组执行分组标识符（PID）过滤。检测包括段数据的传输流分组。使用区段数据的头部信息对相关区段的有效载荷执行CRC处理，并处理帧缓冲。该方法和装置可以使用多个CRC检查器以并行方式执行CRC，而不会在相邻部分之间产生干扰，并且可以执行部分检测和可靠性验证。

7. 发明申请

US20070019761A1 Apparatus and method for receiving broadcasting service in a broadcasting system 有权
标题翻译：在广播系统中接收广播服务的装置和方法
公开(公告)号：US20070019761A1
公开(公告)日：2007-01-25
申请号：US11488645
申请日：2006-07-19
申请人： Sung-Jin Park , Hee-Jin Roh , Min-Goo Kim , Hyun-Seok Oh
发明人： Sung-Jin Park , Hee-Jin Roh , Min-Goo Kim , Hyun-Seok Oh
IPC分类号： H04L27/06
CPC分类号： H04L25/067 , H04L1/0054 , H04L1/0071 , H04L2001/0093
摘要： A broadcasting receiving apparatus and method in a broadcasting system are provided. In a broadcasting receiver, a demodulator demodulates a received broadcasting signal, clips a soft metric value for the demodulated signal to a number of bits, and outputs the clipped soft metric value. A mapper maps the clipped soft metric value to an index value with a resolution inversely proportional to the quantization level of the soft metric value. A deinterleaver deinterleaves the index value and a demapper demaps the deinterleaved index value to a representative value being a soft metric value from a range of soft metric values mapped to the index value. A channel decoder decodes the representative value.
摘要翻译：提供广播系统中的广播接收装置和方法。在广播接收机中，解调器解调所接收的广播信号，将解调信号的软度量值剪除为多个比特，并输出限幅软度量值。映射器将限幅软度量值映射到具有与软度量值的量化级别成反比的分辨率的索引值。解交织器对索引值进行解交织，并且解映射器将解交织的索引值从映射到索引值的软度量值的范围中解映射为作为软度量值的代表值。通道解码器解码代表值。

8. 发明授权

US07656973B2 Apparatus and method for receiving broadcasting service in a broadcasting system 有权
标题翻译：在广播系统中接收广播服务的装置和方法
公开(公告)号：US07656973B2
公开(公告)日：2010-02-02
申请号：US11488645
申请日：2006-07-19
申请人： Sung-Jin Park , Hee-Jin Roh , Min-Goo Kim , Hyun-Seok Oh
发明人： Sung-Jin Park , Hee-Jin Roh , Min-Goo Kim , Hyun-Seok Oh
IPC分类号： H04L27/06
CPC分类号： H04L25/067 , H04L1/0054 , H04L1/0071 , H04L2001/0093
摘要： A broadcasting receiving apparatus and method in a broadcasting system are provided. In a broadcasting receiver, a demodulator demodulates a received broadcasting signal, clips a soft metric value for the demodulated signal to a number of bits, and outputs the clipped soft metric value. A mapper maps the clipped soft metric value to an index value with a resolution inversely proportional to the quantization level of the soft metric value. A deinterleaver deinterleaves the index value and a demapper demaps the deinterleaved index value to a representative value being a soft metric value from a range of soft metric values mapped to the index value. A channel decoder decodes the representative value.
摘要翻译：提供广播系统中的广播接收装置和方法。在广播接收机中，解调器解调所接收的广播信号，将解调信号的软度量值剪除为多个比特，并输出限幅软度量值。映射器将限幅软度量值映射到具有与软度量值的量化级别成反比的分辨率的索引值。解交织器对索引值进行解交织，并且解映射器将解交织的索引值从映射到索引值的软度量值的范围中解映射为作为软度量值的代表值。通道解码器解码代表值。

9. 发明授权

US07584389B2 Turbo decoding apparatus and method 有权
标题翻译： Turbo解码装置及方法
公开(公告)号：US07584389B2
公开(公告)日：2009-09-01
申请号：US10634746
申请日：2003-08-06
申请人： Sung-Jin Park , Min-Goo Kim , Soon-Jae Choi
发明人： Sung-Jin Park , Min-Goo Kim , Soon-Jae Choi
IPC分类号： G06F11/00
CPC分类号： H03M13/3927 , H03M13/2957 , H03M13/296
摘要： This invention relates to a turbo decoding apparatus and method for a communication system. A high-rate memory buffer operating at the same frequency as a turbo decoder is arranged between a memory buffer of a receiver and the turbo decoder. The decoding apparatus reads data bits stored in the memory buffer of the receiver via the high-rate memory buffer, delays the read data bits for a time required in the turbo decoder, and then applies the delayed data bits to a Soft-In Soft-Out (SISO) decoder of the turbo decoder. The memory buffer of the receiver outputs data bits at an operating frequency or clock of the turbo decoder.
摘要翻译：本发明涉及一种用于通信系统的turbo解码装置和方法。在turbo接收机的存储缓冲器和turbo解码器之间设置与turbo解码器相同频率工作的高速率存储器缓冲器。解码装置经由高速率存储器缓冲器读取存储在接收机的存储器缓冲器中的数据位，延迟读取数据位在turbo解码器所需的时间，然后将延迟的数据位应用于软入门软件，（SISO）解码器。接收机的存储器缓冲器以turbo解码器的工作频率或时钟输出数据位。

10. 发明授权

US07373582B2 Apparatus and method for turbo decoding using a variable window size 有权
标题翻译：用于使用可变窗口尺寸进行turbo解码的装置和方法
公开(公告)号：US07373582B2
公开(公告)日：2008-05-13
申请号：US11135633
申请日：2005-05-24
申请人： Sung-Jin Park , Min-Goo Kim , Soon-Jae Choi
发明人： Sung-Jin Park , Min-Goo Kim , Soon-Jae Choi
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/3972
摘要： An apparatus and method for turbo decoding using a variable window size. A control logic block receives information about a code rate of received data bits and a data block size, adjusts a window size according to the code rate information, and computes an initial delay. Delta metric blocks compute delta metrics from input data bits of the block size, wherein the delta metrics represent a transition probability for a path from a state to another state, respectively. An alpha metric block receives a delta metric in synchronization with the initial delay, and computes an alpha metric representing a forward state transition probability in each state. One or more beta metric blocks receive delta metrics according to the adjusted window size, and compute beta metrics representing a backward state transition probability in each state, respectively. A log likelihood ratio (LLR) block receives the alpha metric and the beta metrics in synchronization with the initial delay, and computes LLR values for symbols in an ending state. Code reliability is maintained by using a sliding window structure based on a window size varying with a code rate, while simultaneously reducing a decoding time due to an unnecessary initial delay.
摘要翻译：一种使用可变窗口尺寸进行turbo解码的装置和方法。控制逻辑块接收关于接收到的数据位的码率和数据块大小的信息，根据码率信息调整窗口大小，并计算初始延迟。增量度量块计算来自块大小的输入数据位的增量度量，其中，所述增量度量度分别表示从状态到另一状态的路径的转移概率。 α度量块与初始延迟同步地接收增量度量，并且计算表示每个状态中的前向状态转移概率的α度量。一个或多个β度量块根据调整的窗口大小接收增量度量，并分别计算表示每个状态中的向后状态转移概率的β度量。对数似然比（LLR）块与初始延迟同步地接收α度量和β度量，并且计算处于结束状态的符号的LLR值。通过使用基于以码率变化的窗口尺寸的滑动窗口结构来维持代码可靠性，同时由于不必要的初始延迟而同时减少解码时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式