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1. 发明授权

US07662720B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07662720B2
公开(公告)日：2010-02-16
申请号：US12111633
申请日：2008-04-29
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L21/311
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

2. 发明授权

US07382018B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07382018B2
公开(公告)日：2008-06-03
申请号：US11349287
申请日：2006-02-06
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

3. 发明申请

US20060186446A1 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US20060186446A1
公开(公告)日：2006-08-24
申请号：US11349287
申请日：2006-02-06
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

4. 发明授权

US07768070B2 Semiconductor devices having field effect transistors 有权
标题翻译：具有场效应晶体管的半导体器件
公开(公告)号：US07768070B2
公开(公告)日：2010-08-03
申请号：US11832589
申请日：2007-08-01
申请人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
发明人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.
摘要翻译：一种具有场效应晶体管的半导体器件及其制造方法。通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。原位掺杂的外延图案贯穿整个杂质浓度。因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

5. 发明授权

US07723762B2 Schottky barrier FinFET device and fabrication method thereof 有权
标题翻译：肖特基势垒FinFET器件及其制造方法
公开(公告)号：US07723762B2
公开(公告)日：2010-05-25
申请号：US11598374
申请日：2006-11-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

6. 发明申请

US20050158934A1 Semiconductor devices having field effect transistors and methods of fabricating the same 有权
标题翻译：具有场效应晶体管的半导体器件及其制造方法
公开(公告)号：US20050158934A1
公开(公告)日：2005-07-21
申请号：US11030770
申请日：2005-01-05
申请人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
发明人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L29/423 , H01L29/786 , H01L21/425
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.
摘要翻译：一种具有场效应晶体管的半导体器件及其制造方法。通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。原位掺杂的外延图案贯穿整个杂质浓度。因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

7. 发明申请

US20100197099A1 SCHOTTKY BARRIER FiNFET DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：肖特基屏障器件及其制造方法
公开(公告)号：US20100197099A1
公开(公告)日：2010-08-05
申请号：US12759290
申请日：2010-04-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

8. 发明申请

US20080093664A1 Memory device and method of manufacturing the same 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：US20080093664A1
公开(公告)日：2008-04-24
申请号：US11894449
申请日：2007-08-21
申请人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Dong-Won Kim , Sung-Hwan Kim
发明人： Eun-Jung Yun , Min-Sang Kim , Sung-Min Kim , Dong-Won Kim , Sung-Hwan Kim
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/10876 , H01L27/11 , H01L27/115 , H01L27/11521 , H01L27/11556 , H01L27/11568 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/42356 , H01L29/513 , H01L29/518 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7827 , H01L29/7881 , H01L29/7926
摘要： In a memory device and a method of manufacturing the memory device, the memory device includes a first gate electrode enclosed by a first gate insulating layer, a second gate electrode enclosed by a second gate insulating layer that can be an ONO layer, and a channel region vertically extending between the first gate electrode and the second gate electrode. The first gate electrode is used for removing a charge trapped in the second gate insulating layer. Thus, the memory device can have an improved characteristic when performing an erase operation.
摘要翻译：在存储器件和存储器件的制造方法中，存储器件包括由第一栅极绝缘层包围的第一栅极电极，由可以是ONO层的第二栅极绝缘层包围的第二栅电极，以及通道在第一栅电极和第二栅电极之间垂直延伸的区域。第一栅电极用于去除在第二栅极绝缘层中俘获的电荷。因此，当执行擦除操作时，存储器件可以具有改进的特性。

9. 发明申请

US20070111435A1 Schottky barrier finfet device and fabrication method thereof 有权
标题翻译：肖特基势垒鳍片器件及其制造方法
公开(公告)号：US20070111435A1
公开(公告)日：2007-05-17
申请号：US11598374
申请日：2006-11-13
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim
IPC分类号： H01L21/336 , H01L29/76 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/41791 , H01L29/66795 , H01L29/7839 , H01L29/78618 , H01L29/78684
摘要： A Schottky barrier FinFET device and a method of fabricating the same are provided. The device includes a lower fin body provided on a substrate. An upper fin body having first and second sidewalls which extend upwardly from a center of the lower fin body and face each other is provided. A gate structure crossing over the upper fin body and covering an upper surface of the upper fin body and the first and second sidewalls is provided. The Schottky barrier FinFET device includes a source and a drain which are formed on the sidewalls of the upper fin body adjacent to sidewalls of the gate structure and made of a metal material layer formed on an upper surface of the lower fin body positioned at both sides of the upper fin body, and the source and drain form a Schottky barrier to the lower and upper fin bodies.
摘要翻译：提供肖特基势垒FinFET器件及其制造方法。该装置包括设置在基板上的下部翅片体。提供具有从下翅片体的中心向上延伸并彼此面对的第一和第二侧壁的上翅片本体。提供了一种跨越上翅片体并覆盖上翅片体的上表面和第一和第二侧壁的门结构。肖特基势垒FinFET器件包括源极和漏极，其形成在与鳍结构的侧壁相邻的上翅片体的侧壁上，并且由形成在位于两侧的下翅片体的上表面上的金属材料层并且源极和漏极对下鳍体和上鳍体形成肖特基势垒。

10. 发明授权

US07265418B2 Semiconductor devices having field effect transistors 有权
标题翻译：具有场效应晶体管的半导体器件
公开(公告)号：US07265418B2
公开(公告)日：2007-09-04
申请号：US11030770
申请日：2005-01-05
申请人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
发明人： Eun-Jung Yun , Hye-Jin Cho , Dong-Won Kim , Sung-Min Kim
IPC分类号： H01L27/01 , H01L21/84
CPC分类号： H01L29/785 , H01L21/823437 , H01L29/42384 , H01L29/42392 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device having a field effect transistor and a method of fabricating the same. In-situ doped epitaxial patterns are respectively formed at both sidewalls of a protruded channel pattern from a substrate by performing an in-situ doped epitaxial growth process. The in-situ doped epitaxial pattern has a conformal impurity concentration throughout. Accordingly, source/drain regions with a conformal impurity concentration are connected throughout a channel width of a channel region including both sidewalls of a protruded channel pattern. As a result, it is possible to maximize a driving current of the filed effect transistor, and an on-off characteristic can be highly stabilized.
摘要翻译：一种具有场效应晶体管的半导体器件及其制造方法。通过进行原位掺杂的外延生长工艺，从衬底分别在突出沟道图案的两个侧壁处形成原位掺杂的外延图案。原位掺杂的外延图案贯穿整个杂质浓度。因此，具有共形杂质浓度的源极/漏极区域贯穿包括突出沟道图案的两个侧壁的沟道区域的沟道宽度。结果，可以使场效应晶体管的驱动电流最大化，并且开 - 关特性可以高度稳定。

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