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1. 发明授权

US07662720B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07662720B2
公开(公告)日：2010-02-16
申请号：US12111633
申请日：2008-04-29
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L21/311
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

2. 发明授权

US07382018B2 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US07382018B2
公开(公告)日：2008-06-03
申请号：US11349287
申请日：2006-02-06
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

3. 发明申请

US20060186446A1 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US20060186446A1
公开(公告)日：2006-08-24
申请号：US11349287
申请日：2006-02-06
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

4. 发明申请

US20110220977A1 SEMICONDUCTOR DEVICES WITH BURIED BIT LINES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：带有双绞线的半导体器件及制造半导体器件的方法
公开(公告)号：US20110220977A1
公开(公告)日：2011-09-15
申请号：US12760140
申请日：2010-04-14
申请人： Jae-Man Yoon , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim , Yong-Chul Oh
发明人： Jae-Man Yoon , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim , Yong-Chul Oh
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/336
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10817 , H01L27/10876 , H01L27/10894 , H01L27/1203 , H01L29/7833
摘要： A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line.
摘要翻译：一种半导体器件，包括：形成在绝缘体上硅（SOI））衬底上的垂直立柱晶体管（VPT），所述VPT包括具有下部和上部的主体，设置在上部的源极/漏极节点本体的上部的端部和设置在主体的下部的排水/源节点; 在侧壁和下部的上表面上连续形成的埋置位线（BBL），BBL包括金属微孔; 以及字线，其部分地包围VPT的主体的上部，其中，BBL沿着第一方向延伸，并且字线在基本上垂直于第一方向的第二方向上延伸。偏移区域设置在字线的正下方。

5. 发明授权

US07999309B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07999309B2
公开(公告)日：2011-08-16
申请号：US12385433
申请日：2009-04-08
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0688 , H01L21/8221
摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
摘要翻译：在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案，所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域在半导体图案的上部。

6. 发明授权

US07919378B2 Transistor and method of forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US07919378B2
公开(公告)日：2011-04-05
申请号：US12397176
申请日：2009-03-03
申请人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
发明人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
摘要翻译：根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。活性结构包括在源极/漏极区域下形成阻挡区的沟槽。栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

7. 发明授权

US07902026B2 Method of fabricating semiconductor device having vertical channel transistor 失效
标题翻译：制造具有垂直沟道晶体管的半导体器件的方法
公开(公告)号：US07902026B2
公开(公告)日：2011-03-08
申请号：US12314139
申请日：2008-12-04
申请人： Hyun-Woo Chung , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hyun-Woo Chung , Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/76237 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： A method of fabricating a semiconductor device having a vertical channel transistor, the method including forming a hard mask pattern on a substrate, forming a preliminary active pillar by etching the substrate using the hard mask pattern as an etch mask, reducing a width of the preliminary active pillar to form an active pillar having a width less than that of the hard mask pattern, forming a lower source/drain region by implanting impurity ions into the substrate adjacent to the active pillar using the hard mask pattern as an ion implantation mask, and forming an upper source/drain region on the active pillar and vertically separated from the lower source/drain region.
摘要翻译：一种制造具有垂直沟道晶体管的半导体器件的方法，所述方法包括在衬底上形成硬掩模图案，通过使用硬掩模图案作为蚀刻掩模蚀刻衬底来形成预活性柱，从而减小初步活性柱以形成宽度小于硬掩模图案的有源柱，通过使用硬掩模图案作为离子注入掩模将杂质离子注入邻近有源柱的衬底中来形成下源极/漏极区域，以及在有源柱上形成上部源极/漏极区域，并与下部源极/漏极区域垂直分离。

8. 发明申请

US20100283094A1 SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20100283094A1
公开(公告)日：2010-11-11
申请号：US12840599
申请日：2010-07-21
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

9. 发明申请

US20080003753A1 Semiconductor Device Having Buried Gate Electrode and Method of Fabricating the Same 有权
标题翻译：具有掩埋电极的半导体器件及其制造方法
公开(公告)号：US20080003753A1
公开(公告)日：2008-01-03
申请号：US11608482
申请日：2006-12-08
申请人： Hyeoung-Won Seo , Jae-Man Yoon , Kang-Yoon Lee , Young-Woong Son
发明人： Hyeoung-Won Seo , Jae-Man Yoon , Kang-Yoon Lee , Young-Woong Son
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L29/78
摘要： A semiconductor device includes an isolation layer disposed in a semiconductor device to define an active region. A gate trench is disposed across the active region and extends to the isolation layer. An insulated gate electrode fills a portion of the gate trench and covers at least one sidewall of the active region. A portion of the gate electrode, that covers at least one sidewall of the active region, extends under a portion of the gate electrode that crosses the active region. An insulating pattern is disposed on the gate electrode.
摘要翻译：半导体器件包括设置在半导体器件中以限定有源区的隔离层。栅极沟槽横跨有源区域设置并延伸到隔离层。绝缘栅电极填充栅极沟槽的一部分并覆盖有源区的至少一个侧壁。覆盖有源区的至少一个侧壁的栅电极的一部分在与有源区交叉的栅电极的一部分之下延伸。绝缘图案设置在栅电极上。

10. 发明授权

US07056781B2 Method of forming fin field effect transistor 有权
标题翻译：形成鳍式场效应晶体管的方法
公开(公告)号：US07056781B2
公开(公告)日：2006-06-06
申请号：US11014212
申请日：2004-12-15
申请人： Jae-Man Yoon , Gyo-Young Jin , Hee-Soo Kang , Dong-Gun Park
发明人： Jae-Man Yoon , Gyo-Young Jin , Hee-Soo Kang , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7854 , H01L29/78609
摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.
摘要翻译：根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。侧壁由形成在器件隔离膜上的开口部分部分露出。开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。源极和漏极区域在栅电极不是的有源区域的一部分上。可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。

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