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1. 发明申请

US20130001699A1 TRENCH JUNCTION BARRIER SCHOTTKY STRUCTURE WITH ENHANCED CONTACT AREA INTEGRATED WITH A MOSFET 审中-公开
标题翻译：具有与MOSFET集成的增强接触区的TRENCH JUNCTION BARRIER SCHOTTKY STRUCTURE WITH ENHANCED CONTACT AREA
公开(公告)号：US20130001699A1
公开(公告)日：2013-01-03
申请号：US13171475
申请日：2011-06-29
申请人： Sung-Shan Tai , Po-Hsien Li , Guo-Liang Yang , Shian Hau Liao
发明人： Sung-Shan Tai , Po-Hsien Li , Guo-Liang Yang , Shian Hau Liao
IPC分类号： H01L27/06 , H01L21/283
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/0623 , H01L29/1095 , H01L29/41708 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/782 , H01L29/872
摘要： An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.
摘要翻译：本发明的目的是提供一种肖特基二极管结构，以增加肖特基势垒金属与半导体衬底之间的肖特基结的接触面积。肖特基结的接触面积越大，肖特基二极管的正向压降越低，从而提高肖特基二极管的性能和效率。本发明还公开了具有相邻顶部台面的多个沟槽可用于形成具有甚至更大接触面积的肖特基二极管，其中使用MOSFET的两个单元之间的隔离区域构建沟槽，并以最小的额外开销来缩小尺寸在两个沟槽之间的间距。

2. 发明授权

US08178923B2 Power semiconductor device having low gate input resistance 有权
标题翻译：具有低栅极输入电阻的功率半导体器件
公开(公告)号：US08178923B2
公开(公告)日：2012-05-15
申请号：US12840283
申请日：2010-07-20
申请人： Wei-Chieh Lin , Guo-Liang Yang , Jia-Fu Lin , Shian-Hau Liao
发明人： Wei-Chieh Lin , Guo-Liang Yang , Jia-Fu Lin , Shian-Hau Liao
IPC分类号： H01L23/48
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/4925 , H01L29/66727 , H01L29/66734
摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.
摘要翻译：提供了具有低栅极输入电阻的功率半导体器件及其制造方法。功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

3. 发明授权

US08362529B2 Power semiconductor device having adjustable output capacitance 有权
标题翻译：具有可调输出电容的功率半导体器件
公开(公告)号：US08362529B2
公开(公告)日：2013-01-29
申请号：US12784505
申请日：2010-05-21
申请人： Wei-Chieh Lin , Guo-Liang Yang , Shian-Hau Liao
发明人： Wei-Chieh Lin , Guo-Liang Yang , Shian-Hau Liao
IPC分类号： H01L29/76
CPC分类号： H01L27/06 , H01L29/739
摘要： A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.
摘要翻译：具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层。第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

4. 发明申请

US20110291183A1 POWER SEMICONDUCTOR DEVICE HAVING LOW GATE INPUT RESISTANCE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有低栅极输入电阻的功率半导体器件及其制造方法
公开(公告)号：US20110291183A1
公开(公告)日：2011-12-01
申请号：US12840283
申请日：2010-07-20
申请人： Wei-Chieh Lin , Guo-Liang Yang , Jia-Fu Lin , Shian-Hau Liao
发明人： Wei-Chieh Lin , Guo-Liang Yang , Jia-Fu Lin , Shian-Hau Liao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/4925 , H01L29/66727 , H01L29/66734
摘要： A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.
摘要翻译：提供了具有低栅极输入电阻的功率半导体器件及其制造方法。功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

5. 发明申请

US20110215374A1 POWER SEMICONDUCTOR DEVICE HAVING ADJUSTABLE OUTPUT CAPACITANCE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有可调输出电容的功率半导体器件及其制造方法
公开(公告)号：US20110215374A1
公开(公告)日：2011-09-08
申请号：US12784505
申请日：2010-05-21
申请人： Wei-Chieh Lin , Guo-Liang Yang , Shian-Hau Liao
发明人： Wei-Chieh Lin , Guo-Liang Yang , Shian-Hau Liao
IPC分类号： H01L27/06 , H01L29/739 , H01L21/336
CPC分类号： H01L27/06 , H01L29/739
摘要： A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.
摘要翻译：具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层。第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

6. 发明授权

US08198684B2 Semiconductor device with drain voltage protection for ESD 有权
标题翻译：具有ESD保护漏极电压的半导体器件
公开(公告)号：US08198684B2
公开(公告)日：2012-06-12
申请号：US12614434
申请日：2009-11-08
申请人： Wei-Chieh Lin , Guo-Liang Yang , Jen-Hao Yeh , Jia-Fu Lin
发明人： Wei-Chieh Lin , Guo-Liang Yang , Jen-Hao Yeh , Jia-Fu Lin
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L23/60 , H01L24/05 , H01L27/0255 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.
摘要翻译：具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。半导体衬底的上表面具有第一沟槽和第二沟槽。沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

7. 发明申请

US20110084335A1 SEMICONDUCTOR DEVICE WITH DRAIN VOLTAGE PROTECTION AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有漏电保护的半导体器件及其制造方法
公开(公告)号：US20110084335A1
公开(公告)日：2011-04-14
申请号：US12614434
申请日：2009-11-08
申请人： Wei-Chieh Lin , Guo-Liang Yang , Jen-Hao Yeh , Jia-Fu Lin
发明人： Wei-Chieh Lin , Guo-Liang Yang , Jen-Hao Yeh , Jia-Fu Lin
IPC分类号： H01L27/06 , H01L21/8234 , H01L23/60
CPC分类号： H01L27/0629 , H01L23/60 , H01L24/05 , H01L27/0255 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.
摘要翻译：具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。半导体衬底的上表面具有第一沟槽和第二沟槽。沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

8. 发明授权

US08241978B2 Method of manufacturing semiconductor device having integrated MOSFET and Schottky diode 有权
标题翻译：具有集成MOSFET和肖特基二极管的半导体器件的制造方法
公开(公告)号：US08241978B2
公开(公告)日：2012-08-14
申请号：US12536504
申请日：2009-08-06
申请人： Wei-Chieh Lin , Li-Cheng Lin , Hsin-Yu Hsu , Ho-Tai Chen , Jen-Hao Yeh , Guo-Liang Yang , Chia-Hui Chen , Shih-Chieh Hung
发明人： Wei-Chieh Lin , Li-Cheng Lin , Hsin-Yu Hsu , Ho-Tai Chen , Jen-Hao Yeh , Guo-Liang Yang , Chia-Hui Chen , Shih-Chieh Hung
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L27/0629 , H01L29/8725
摘要： A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.
摘要翻译：具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。

9. 发明授权

US07867854B2 Method of fabricating power semiconductor device 有权
标题翻译：制造功率半导体器件的方法
公开(公告)号：US07867854B2
公开(公告)日：2011-01-11
申请号：US12507808
申请日：2009-07-23
申请人： Wei-Chieh Lin , Hsin-Yu Hsu , Guo-Liang Yang , Jen-Hao Yeh
发明人： Wei-Chieh Lin , Hsin-Yu Hsu , Guo-Liang Yang , Jen-Hao Yeh
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/1095 , H01L29/4236 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.
摘要翻译：在衬底中形成更宽且更窄的沟槽。沉积第一栅极材料层，但不完全填充较宽的沟槽。通过各向同性或各向异性蚀刻来去除较宽沟槽中的第一栅极材料层和衬底原始表面之上。第一掺杂剂层通过倾斜离子注入在原始表面和较宽沟槽的侧壁和底部形成在衬底的表面层中。沉积第二栅极材料层以完全填充沟槽。通过各向异性蚀刻去除原始表面上方的栅极材料层。通过离子注入在原始表面的基板的表面层中形成第二掺杂剂层。掺杂剂被驱入以在衬底中形成基底，并且围绕较宽沟槽的底部并且与基底相邻的底部轻掺杂层。

10. 发明授权

US08120100B2 Overlapping trench gate semiconductor device 有权
标题翻译：重叠沟槽栅极半导体器件
公开(公告)号：US08120100B2
公开(公告)日：2012-02-21
申请号：US12616770
申请日：2009-11-11
申请人： Wei-Chieh Lin , Jen-Hao Yeh , Guo-Liang Yang , Jia-Fu Lin
发明人： Wei-Chieh Lin , Jen-Hao Yeh , Guo-Liang Yang , Jia-Fu Lin
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.
摘要翻译：重叠沟槽栅极半导体器件包括半导体衬底，设置在半导体衬底上的多个浅沟槽，设置在浅沟槽中的第一导电层，分别设置在每个浅沟槽中的多个深沟槽，设置在第二导电层中的第二导电层深沟槽，源极金属层和栅极金属层。每个深沟槽在每个浅沟槽下延伸到半导体衬底中。源极金属层电连接到第二导电层，并且栅极金属层电连接到第一导电层。

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