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1. 发明申请

US20130001699A1 TRENCH JUNCTION BARRIER SCHOTTKY STRUCTURE WITH ENHANCED CONTACT AREA INTEGRATED WITH A MOSFET 审中-公开
标题翻译：具有与MOSFET集成的增强接触区的TRENCH JUNCTION BARRIER SCHOTTKY STRUCTURE WITH ENHANCED CONTACT AREA
公开(公告)号：US20130001699A1
公开(公告)日：2013-01-03
申请号：US13171475
申请日：2011-06-29
申请人： Sung-Shan Tai , Po-Hsien Li , Guo-Liang Yang , Shian Hau Liao
发明人： Sung-Shan Tai , Po-Hsien Li , Guo-Liang Yang , Shian Hau Liao
IPC分类号： H01L27/06 , H01L21/283
CPC分类号： H01L29/7813 , H01L27/0629 , H01L29/0623 , H01L29/1095 , H01L29/41708 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/782 , H01L29/872
摘要： An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.
摘要翻译：本发明的目的是提供一种肖特基二极管结构，以增加肖特基势垒金属与半导体衬底之间的肖特基结的接触面积。肖特基结的接触面积越大，肖特基二极管的正向压降越低，从而提高肖特基二极管的性能和效率。本发明还公开了具有相邻顶部台面的多个沟槽可用于形成具有甚至更大接触面积的肖特基二极管，其中使用MOSFET的两个单元之间的隔离区域构建沟槽，并以最小的额外开销来缩小尺寸在两个沟槽之间的间距。

2. 发明授权

US08536646B2 Trench type power transistor device 有权
标题翻译：沟槽型功率晶体管器件
公开(公告)号：US08536646B2
公开(公告)日：2013-09-17
申请号：US13237940
申请日：2011-09-21
申请人： Teng-Hao Yeh , Shian-Hau Liao , Chia-Hui Chen , Sung-Shan Tai
发明人： Teng-Hao Yeh , Shian-Hau Liao , Chia-Hui Chen , Sung-Shan Tai
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： The present invention provides a trench type power transistor device including a semiconductor substrate, at least one transistor cell, a gate metal layer, a source metal layer, and a second gate conductive layer. The semiconductor substrate has at least one trench. The transistor cell includes a first gate conductive layer disposed in the trench. The gate metal layer and the source metal layer are disposed on the semiconductor substrate. The second gate conductive layer is disposed between the first gate conductive layer and the source metal layer. The second gate conductive layer electrically connects the first gate conductive layer to the gate metal layer, and the second gate conductive layer is electrically insulated from the source metal layer and the semiconductor substrate.
摘要翻译：本发明提供了包括半导体衬底，至少一个晶体管单元，栅极金属层，源极金属层和第二栅极导电层的沟槽型功率晶体管器件。半导体衬底具有至少一个沟槽。晶体管单元包括设置在沟槽中的第一栅极导电层。栅极金属层和源极金属层设置在半导体衬底上。第二栅极导电层设置在第一栅极导电层和源极金属层之间。第二栅极导电层将第一栅极导电层电连接到栅极金属层，并且第二栅极导电层与源极金属层和半导体衬底电绝缘。

3. 发明申请

US20170288034A1 DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK 审中-公开
公开(公告)号：US20170288034A1
公开(公告)日：2017-10-05
申请号：US15499487
申请日：2017-04-27
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/423 , H01L29/06 , H01L29/40 , H01L27/088
CPC分类号： H01L29/42368 , H01L27/088 , H01L29/0619 , H01L29/401 , H01L29/4236
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

4. 发明授权

US08709895B2 Manufacturing method power semiconductor device 有权
标题翻译：制造方法功率半导体器件
公开(公告)号：US08709895B2
公开(公告)日：2014-04-29
申请号：US13038346
申请日：2011-03-01
申请人： Sung-Shan Tai , Hung-Sheng Tsai
发明人： Sung-Shan Tai , Hung-Sheng Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0638 , H01L29/0653 , H01L29/0661 , H01L29/0696 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.
摘要翻译：本发明提供一种功率半导体器件的端接结构及其制造方法。功率半导体器件具有有源区和端接区。终端区域围绕有源区域，终端结构设置在终端区域中。端接结构包括半导体衬底，绝缘层和金属层。半导体衬底具有设置在终端区域中的沟槽。绝缘层部分地填充到沟槽中并且覆盖半导体衬底，并且绝缘层的顶表面具有孔。金属层设置在绝缘层上，并被填充到孔中。

5. 发明授权

US08471368B2 Polysilicon control etch back indicator 失效
标题翻译：多晶硅控制回蚀指示器
公开(公告)号：US08471368B2
公开(公告)日：2013-06-25
申请号：US13431551
申请日：2012-03-27
申请人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
发明人： Yu Wang , Tiesheng Li , Sung-Shan Tai , Hong Chang
IPC分类号： H01L29/06
CPC分类号： H01L29/7813 , H01L22/12 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.
摘要翻译：本发明公开了一种用于在其上制造电子电路的半导体晶片。半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部具有较小的平面沟槽尺寸。

6. 发明申请

US20130049104A1 Method of forming a self-aligned contact opening in MOSFET 有权
标题翻译：在MOSFET中形成自对准接触开口的方法
公开(公告)号：US20130049104A1
公开(公告)日：2013-02-28
申请号：US13218476
申请日：2011-08-26
申请人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
发明人： Sung-Shan Tai , Teng-hao Yeh , Chia-Hui Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L21/3105
CPC分类号： H01L29/7813 , H01L29/41741 , H01L29/41766 , H01L29/41775 , H01L29/66719 , H01L29/66727 , H01L29/66734
摘要： A method of forming a contact opening in a semiconductor substrate is presented. A plurality of trench gates each having a projecting portion are formed in a semiconductor substrate, and a stop layer is deposited over the semiconductor substrate extending over the projecting portions, wherein each portion of the stop layer along each of the sidewalls of the projecting portions is covered by a spacer. By removing the portions of the stop layer not covered by the spacers by utilizing a relatively higher etching selectivity of the stop layer to the spacers, the openings between adjacent projecting portions with an L-type shape on each sidewall can be formed, and a lithography process can be performed to form self-aligned contact openings thereafter.
摘要翻译：提出了在半导体衬底中形成接触开口的方法。在半导体衬底中形成各自具有突出部分的多个沟槽栅极，并且在突出部分上延伸的半导体衬底上沉积停止层，其中沿着突出部分的每个侧壁的阻挡层的每个部分是被间隔物覆盖。通过利用阻挡层对间隔物的相对较高的蚀刻选择性去除未被间隔物覆盖的停止层的部分，可以形成每个侧壁上具有L型形状的相邻突出部分之间的开口，并且可以形成光刻此后可以进行处理以形成自对准的接触开口。

7. 发明授权

US08048775B2 Process of forming ultra thin wafers having an edge support ring 有权
公开(公告)号：US08048775B2
公开(公告)日：2011-11-01
申请号：US11880455
申请日：2007-07-20
申请人： Tao Feng , Sung-Shan Tai
发明人： Tao Feng , Sung-Shan Tai
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/02035 , H01L21/02013 , H01L21/3043 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

8. 发明申请

US20110223742A1 Process of forming ultra thin wafers having an edge support ring 有权
标题翻译：形成具有边缘支撑环的超薄晶片的工艺
公开(公告)号：US20110223742A1
公开(公告)日：2011-09-15
申请号：US13115097
申请日：2011-05-24
申请人： Tao Feng , Sung-Shan Tai
发明人： Tao Feng , Sung-Shan Tai
IPC分类号： H01L21/304
CPC分类号： H01L21/02035 , H01L21/02013 , H01L21/3043 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.
摘要翻译：公开了一种形成具有边缘支撑环的超薄晶片的工艺。该工艺提供了具有与旋转蚀刻工艺兼容的成角度的内壁的边缘支撑环。

9. 发明申请

US20110042724A1 Trenched mosfets with part of the device formed on a (110) crystal plane 审中-公开
标题翻译：在110平面上形成有部分器件的沟槽式mosfet
公开(公告)号：US20110042724A1
公开(公告)日：2011-02-24
申请号：US11634031
申请日：2009-04-20
申请人： Anup Bhalla , Sik K. Lui , Sung-Shan Tai
发明人： Anup Bhalla , Sik K. Lui , Sung-Shan Tai
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L24/33 , H01L29/045 , H01L29/4236 , H01L29/66734 , H01L29/7811 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming the sidewalls of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.
摘要翻译：本发明公开了通过在半导体衬底的（110）晶体取向上形成沟槽的侧壁而制造的具有沟槽栅极的改进的MOSFET器件。沟槽沿着沿着半导体衬底的不同晶体取向形成的沟槽的侧壁和底表面或沟槽的终端覆盖电介质氧化物层。实施诸如氧化物退火工艺，特殊掩模或SOG工艺的特殊制造工艺以克服非均匀介电层生长的限制。

10. 发明授权

US07667264B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US07667264B2
公开(公告)日：2010-02-23
申请号：US10952231
申请日：2004-09-27
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：半导体器件包括漏极，与漏极接触的主体，主体具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中，延伸穿过源和主体的沟槽并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

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