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1. 发明授权

US09001569B1 Input trigger independent low leakage memory circuit 有权
标题翻译：输入触发独立低泄漏存储电路
公开(公告)号：US09001569B1
公开(公告)日：2015-04-07
申请号：US14035778
申请日：2013-09-24
申请人： Synopsys, Inc.
发明人： Sanjeev Kumar Jain , Vikas Gadi , Amit Khanuja
IPC分类号： G11C11/00 , G11C8/08 , G11C11/413 , G11C8/10
CPC分类号： G11C8/08 , G11C8/10 , G11C11/418
摘要： Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode). Alternatively, or in addition, source-biasing circuitry applies a relatively high source-biasing voltage to the source terminals of memory cells in unselected columns during read/write operations based on column address values (i.e., a low source voltage is applied only to the selected column being written to or read from).
摘要翻译：字线驱动器偏置和基于列的源极偏置电路有助于减少电流泄漏，例如在独立于读/写/待机操作模式并且没有外部触发的方式下，在SoC器件SRAM电路中。在读/写操作期间，字线驱动器偏置电路关闭（即，与系统电源脱耦）字线驱动器，其中使用响应于行地址值生成的解码器使能信号之一连接到未选择的字线，或者基于激活自身定时内部时钟（由从待机切换到读/写模式）由存储器电路产生的内部时钟的激活。或者或另外，源极偏置电路基于列地址值在读/写操作期间向非选择列中的存储器单元的源极端子施加相对较高的源极偏置电压（即，仅将低源极电压施加到所选列被写入或读取）。

2. 发明授权

US08837229B1 Circuit for generating negative bitline voltage 有权
标题翻译：用于产生负位线电压的电路
公开(公告)号：US08837229B1
公开(公告)日：2014-09-16
申请号：US13958284
申请日：2013-08-02
申请人： Synopsys, Inc.
发明人： Prashant Dubey , Guarav Ahuja , Sanjay Kumar Yadav , Amit Khanuja
IPC分类号： G11C7/00 , G11C7/12 , H02M3/07 , G11C7/10
CPC分类号： G11C7/12 , G11C7/1084 , G11C7/1096 , G11C11/417 , H02M3/07
摘要： An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme.
摘要翻译：用于产生负位线电压的集成电路包括可连接到存储器单元的位线和连接到位线的多个电容器组。步进信号发生器可以产生要施加到一组电容器的步进信号的连续序列。电路可以是集成存储器电路器件的一部分，以将位线驱动到负电压以实现写辅助方案。

3. 发明授权

US09842642B2 Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories 有权
公开(公告)号：US09842642B2
公开(公告)日：2017-12-12
申请号：US14828364
申请日：2015-08-17
申请人： Synopsys, Inc.
发明人： M. Sultan M. Siddiqui , Shailendra Sharad , Hemant Vats , Amit Khanuja
IPC分类号： G11C7/22 , G11C11/419 , G11C11/418 , G11C8/08
CPC分类号： G11C11/419 , G11C7/227 , G11C8/08 , G11C11/418 , G11C2207/229
摘要： An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.

4. 发明申请

US20150170721A1 Controlling Timing of Negative Charge Injection to Generate Reliable Negative Bitline Voltage 有权
标题翻译：控制负电荷注入的时序以产生可靠的负位线电压
公开(公告)号：US20150170721A1
公开(公告)日：2015-06-18
申请号：US14178099
申请日：2014-02-11
申请人： Synopsys, Inc.
发明人： Prashant Dubey , Vaibhav Verma , Gaurav Ahuja , Sanjay Kumar Yadav , Amit Khanuja
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/04 , G11C11/419
摘要： Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.
摘要翻译：实施例涉及通过控制用于启动将负电荷注入到位线的触发信号的延迟来防止或减轻存储器位单元的位线的负电压电平的过度下降。写辅助电路响应于接收到指示位线的负值的数据输入而使负电荷逐渐下降。当电源电压高时，触发信号的定时延迟减小，从而在位线电压保持在较高的电压电平以及位线电压下降到接地电压之前，使负电荷注入位线。由于在位线电压电平相对较高时注入负电荷，即使当电源电压相对较高时，也可防止位线被下拉到过大的负电压电平。

5. 发明申请

US20150085566A1 INPUT TRIGGER INDEPENDENT LOW LEAKAGE MEMORY CIRCUIT 有权
标题翻译：输入触发器独立的低漏电存储器电路
公开(公告)号：US20150085566A1
公开(公告)日：2015-03-26
申请号：US14035778
申请日：2013-09-24
申请人： Synopsys, Inc.
发明人： Sanjeev Kumar Jain , Vikas Gadi , Amit Khanuja
IPC分类号： G11C8/08 , G11C8/10 , G11C11/413
CPC分类号： G11C8/08 , G11C8/10 , G11C11/418
摘要： Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in SoC device SRAM circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode). Alternatively, or in addition, source-biasing circuitry applies a relatively high source-biasing voltage to the source terminals of memory cells in unselected columns during read/write operations based on column address values (i.e., a low source voltage is applied only to the selected column being written to or read from).
摘要翻译：字线驱动器偏置和基于列的源极偏置电路有助于减少电流泄漏，例如在独立于读/写/待机操作模式并且没有外部触发的方式下，在SoC器件SRAM电路中。在读/写操作期间，字线驱动器偏置电路关闭（即，与系统电源脱耦）字线驱动器，其中使用响应于行地址值生成的解码器使能信号之一连接到未选择的字线，或者基于激活自身定时内部时钟（由从待机切换到读/写模式）由存储器电路产生的内部时钟的激活。或者或另外，源极偏置电路基于列地址值在读/写操作期间向非选择列中的存储器单元的源极端子施加相对高的源极偏置电压（即，仅将低源极电压施加到所选列被写入或读取）。

6. 发明授权

US11302365B2 Area efficient and high-performance wordline segmented architecture 有权
公开(公告)号：US11302365B2
公开(公告)日：2022-04-12
申请号：US16583657
申请日：2019-09-26
申请人： Synopsys, Inc.
发明人： Vinay Kumar , Neeraj Kapoor , Sudhir Kumar , Amit Khanuja
IPC分类号： G11C11/418 , G11C5/06 , G11C11/412
摘要： A memory array including a plurality of memory cells and a plurality of drivers is disclosed. The plurality of memory cells may be arranged in a plurality of rows and a plurality of columns. Memory cells corresponding to a row of the plurality of rows may be logically grouped into a plurality of memory array segments. The plurality of drivers may be coupled to corresponding first ends of corresponding memory array segments of the plurality of memory array segments. Second ends of the corresponding memory array segments may be coupled to second ends of corresponding adjacent memory array segments of the plurality of memory array segments. The second ends of the corresponding memory array segments and the second ends of corresponding adjacent memory array segments may be coupled to corresponding wordlines of a plurality of wordlines.

7. 发明授权

US09281030B2 Controlling timing of negative charge injection to generate reliable negative bitline voltage 有权
标题翻译：控制负电荷注入的时序，产生可靠的负位线电压
公开(公告)号：US09281030B2
公开(公告)日：2016-03-08
申请号：US14178099
申请日：2014-02-11
申请人： Synopsys, Inc.
发明人： Prashant Dubey , Vaibhav Verma , Gaurav Ahuja , Sanjay Kumar Yadav , Amit Khanuja
IPC分类号： G11C7/00 , G11C7/12 , G11C11/419 , G11C7/04
CPC分类号： G11C7/12 , G11C7/04 , G11C11/419
摘要： Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.
摘要翻译：实施例涉及通过控制用于启动将负电荷注入到位线的触发信号的延迟来防止或减轻存储器位单元的位线的负电压电平的过度下降。写辅助电路响应于接收到指示位线的负值的数据输入而使负电荷逐渐下降。当电源电压高时，触发信号的定时延迟减小，从而在位线电压保持在较高的电压电平以及位线电压下降到接地电压之前，使负电荷注入位线。由于在位线电压电平相对较高时注入负电荷，即使当电源电压相对较高时，也可防止位线被下拉到过大的负电压电平。

8. 发明申请

US20140269105A1 CIRCUIT FOR GENERATING NEGATIVE BITLINE VOLTAGE 有权
标题翻译：用于产生负电位电压的电路
公开(公告)号：US20140269105A1
公开(公告)日：2014-09-18
申请号：US13958284
申请日：2013-08-02
申请人： Synopsys, Inc.
发明人： Prashant Dubey , Guarav Ahuja , Sanjay Kumar Yadav , Amit Khanuja
IPC分类号： G11C7/12 , H02M3/07
CPC分类号： G11C7/12 , G11C7/1084 , G11C7/1096 , G11C11/417 , H02M3/07
摘要： An integrated circuit for generating a negative bitline voltage comprises a bitline connectable to a memory cell and a multitude of capacitors arranged in groups thereof connected to the bitline. A step signal generator can generate a consecutive sequence of step signals to be applied to a group of capacitors. The circuit may be part of an integrated memory circuit device to drive the bitline to a negative voltage to implement a write assist scheme.
摘要翻译：用于产生负位线电压的集成电路包括可连接到存储器单元的位线和连接到位线的多个电容器组。步进信号发生器可以产生要施加到一组电容器的步进信号的连续序列。电路可以是集成存储器电路器件的一部分，以将位线驱动到负电压以实现写辅助方案。

9. 发明授权

US11574675B2 Temperature tracked dynamic keeper implementation to enable read operations 有权
公开(公告)号：US11574675B2
公开(公告)日：2023-02-07
申请号：US17133103
申请日：2020-12-23
申请人： Synopsys, Inc.
发明人： Vinay Kumar , Saurabh Porwal , Sudhir Kumar , Madhav Mansukh Padaliya , Amit Khanuja
IPC分类号： G11C11/419 , G11C11/418
摘要： A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second keeper based on temperature.

10. 发明申请

US20210193219A1 Temperature Tracked Dynamic Keeper Implementation to Enable Read Operations 有权
公开(公告)号：US20210193219A1
公开(公告)日：2021-06-24
申请号：US17133103
申请日：2020-12-23
申请人： Synopsys, Inc.
发明人： Vinay Kumar , Saurabh Porwal , Sudhir Kumar , Madhav Mansukh Padaliya , Amit Khanuja
IPC分类号： G11C11/419 , G11C11/418
摘要： A static random access memory (SRAM) system includes a plurality of SRAM storage cells, each of the plurality of SRAM storage cells coupled to a respective read bit line, and a dynamic keeper coupled to the read bit line. The dynamic keeper includes a first keeper to support a read operation at a first temperature range, and a second keeper to support the read operation at a second temperature range, and a temperature-sensitive control circuit to select the first keeper or the second keeper based on temperature.

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