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1. 发明申请

US20160049191A1 Integrated Circuit for Storing Data 有权
标题翻译：用于存储数据的集成电路
公开(公告)号：US20160049191A1
公开(公告)日：2016-02-18
申请号：US14828364
申请日：2015-08-17
申请人： Synopsys, Inc.
发明人： Sultan M. Siddiqui , Shailendra Sharad , Hemant Vats , Amit Khanuja
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C7/227 , G11C8/08 , G11C11/418 , G11C2207/229
摘要： An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.
摘要翻译：一种用于存储数据的集成电路包括存储单元阵列，该存储单元阵列包括多个位单元（BC1，...，BCn），其包括具有静态随机存取存储器体系结构的第一和第二位单元（BC1，BC2）。第一和第二位单元（BC1，BC2）耦合到公共字线（WL_TOP），并被布置在存储单元阵列（100）的不同列（C1，C2）中。在对第一位单元（BC1）的写访问期间，第一位单元（BC1）进行写操作，而第二位单元（BC2）是进行伪读操作的半选位单元。该集成电路采用两相写入方案来提高低工作电压环境下的写入能力。

2. 发明授权

US09842642B2 Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories 有权
公开(公告)号：US09842642B2
公开(公告)日：2017-12-12
申请号：US14828364
申请日：2015-08-17
申请人： Synopsys, Inc.
发明人： M. Sultan M. Siddiqui , Shailendra Sharad , Hemant Vats , Amit Khanuja
IPC分类号： G11C7/22 , G11C11/419 , G11C11/418 , G11C8/08
CPC分类号： G11C11/419 , G11C7/227 , G11C8/08 , G11C11/418 , G11C2207/229
摘要： An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.

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