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1. 发明申请

US20230128141A1 HEADER CIRCUIT PLACEMENT IN MEMORY DEVICE 有权
公开(公告)号：US20230128141A1
公开(公告)日：2023-04-27
申请号：US18088216
申请日：2022-12-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Po-Sheng Wang , Yangsyu Lin , Kao-Cheng Lin , Cheng Hung Lee , Jonathan Tsung-Yung Chang
IPC分类号： G11C5/14 , G11C16/30
摘要： Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.

2. 发明申请

US20220319631A1 MEMORY DEVICE AND ELECTRONIC DEVICE 有权
公开(公告)号：US20220319631A1
公开(公告)日：2022-10-06
申请号：US17843591
申请日：2022-06-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Yu Huang , Chia-En Huang , Cheng Hung Lee , Hua-Tai Shieh
IPC分类号： G11C29/00 , G06F11/16 , G11C8/10 , G11C7/12
摘要： Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.

3. 发明授权

US11367507B2 Memory device and electronic device 有权
公开(公告)号：US11367507B2
公开(公告)日：2022-06-21
申请号：US17135043
申请日：2020-12-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Yu Huang , Chia-En Huang , Cheng Hung Lee , Hua-Tai Shieh
IPC分类号： G11C29/00 , G06F11/16 , G11C8/10 , G11C7/12
摘要： Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.

4. 发明授权

US09852249B2 Modified design rules to improve device performance 有权
公开(公告)号：US09852249B2
公开(公告)日：2017-12-26
申请号：US13949683
申请日：2013-07-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
IPC分类号： G06F17/00 , G06F17/50 , H01L27/088 , H01L27/02
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

5. 发明授权

US09666253B2 Dual rail memory, memory macro and associated hybrid power supply method 有权
公开(公告)号：US09666253B2
公开(公告)日：2017-05-30
申请号：US14924069
申请日：2015-10-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Jonathan Tsung-Yung Chang , Chiting Cheng , Cheng Hung Lee , Hung-Jen Liao , Michael Clinton
IPC分类号： G11C7/12 , G11C5/14 , G11C7/10 , G11C7/06 , G11C7/22 , G11C8/10 , G11C8/06 , G11C8/08
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C7/06 , G11C7/065 , G11C7/10 , G11C7/22 , G11C8/06 , G11C8/08 , G11C8/10 , G11C11/417 , G11C11/418
摘要： A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

6. 发明授权

US09484084B2 Pulling devices for driving data lines 有权
标题翻译：拉动设备来驱动数据线
公开(公告)号：US09484084B2
公开(公告)日：2016-11-01
申请号：US14920209
申请日：2015-10-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hao-I Yang , Chia-En Huang , Cheng Hung Lee , Geng-Cing Lin , Jung-Ping Yang
IPC分类号： G11C7/00 , G11C11/419 , G11C7/10 , G11C8/06 , G11C8/18 , G11C7/18 , G11C7/22
CPC分类号： G11C11/419 , G11C7/10 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/06 , G11C8/18 , H01L27/1104 , H01L27/1116
摘要： A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated.
摘要翻译：电路包括第一数据线，第二数据线，第一牵引装置，第二牵引装置，第三牵引装置和第四牵引装置。第一牵引装置被配置为响应于第一控制信号被激活或停用; 并且被配置为当第一牵引装置被激活时，基于第二数据线处的第二信号将第一数据线处的第一信号拉向第一电压的电压电平。第二牵引装置被配置为响应于第二控制信号被激活或停用; 并且被配置为当第二拉动装置被启动时，基于第一数据线处的第一信号将第二数据线处的第二信号拉向第一电压的电压电平。

7. 发明授权

US08605535B2 Integrated circuits, systems, and methods for reducing leakage currents in a retention mode 有权
标题翻译：用于在保持模式下减少漏电流的集成电路，系统和方法
公开(公告)号：US08605535B2
公开(公告)日：2013-12-10
申请号：US13646140
申请日：2012-10-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yen-Huei Chen , Cheng Hung Lee
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C11/412
摘要： A memory array including at least one cross-latched pair of transistors for storing data. The memory array further includes a first power line for supplying a first reference voltage and a second power line for supplying a second reference voltage. The memory array further includes a first switch having a first output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the first power line. The memory array further includes a second switch having a second output coupled with the at least one cross-latched pair of transistors for selectively connecting the at least one cross-latched pair of transistors to the second power line. The first output is coupled to the second output.
摘要翻译：一种包括用于存储数据的至少一个交叉锁存晶体管对的存储器阵列。存储器阵列还包括用于提供第一参考电压的第一电源线和用于提供第二参考电压的第二电源线。存储器阵列还包括具有与至少一个交叉锁存晶体管耦合的第一输出的第一开关，用于选择性地将至少一个交叉锁存的晶体管对连接到第一电力线。存储器阵列还包括具有与至少一个交叉锁存晶体管耦合的第二输出的第二开关，用于选择性地将至少一个交叉锁存的晶体管对连接到第二电力线。第一输出耦合到第二输出。

8. 发明授权

US11133039B2 Power switch control in a memory device 有权
公开(公告)号：US11133039B2
公开(公告)日：2021-09-28
申请号：US16594779
申请日：2019-10-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hao-I Yang , Cheng Hung Lee , Chen-Lin Yang , Yu-Hao Hsu
IPC分类号： G11C5/14 , G11C11/417
摘要： A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.

9. 发明授权

US10951200B2 Clock circuit and method of operating the same 有权
公开(公告)号：US10951200B2
公开(公告)日：2021-03-16
申请号：US16800981
申请日：2020-02-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hao-I Yang , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Yangsyu Lin
IPC分类号： H03K3/037 , G11C11/412 , G06F1/04 , G11C7/22 , G11C11/417
摘要： A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

10. 发明授权

US10340897B2 Clock generating circuit and method of operating the same 有权
公开(公告)号：US10340897B2
公开(公告)日：2019-07-02
申请号：US16039824
申请日：2018-07-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hao-I Yang , Cheng Hung Lee , Chen-Lin Yang , Chiting Cheng , Fu-An Wu , Yangsyu Lin
IPC分类号： H03K3/037 , G11C11/412
摘要： A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.

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