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1. 发明授权

US09852249B2 Modified design rules to improve device performance 有权
公开(公告)号：US09852249B2
公开(公告)日：2017-12-26
申请号：US13949683
申请日：2013-07-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
IPC分类号： G06F17/00 , G06F17/50 , H01L27/088 , H01L27/02
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

2. 发明授权

US09779801B2 Method and control circuit for memory macro 有权
公开(公告)号：US09779801B2
公开(公告)日：2017-10-03
申请号：US14598272
申请日：2015-01-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Annie-Li-Keow Lum
IPC分类号： G11C8/16 , G11C11/419 , G11C7/22
CPC分类号： G11C11/419 , G11C7/227 , G11C8/16
摘要： A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.

3. 发明申请

US20160188654A1 RULE BASED DATA NORMALIZATION UTILIZING MULTI-KEY SORTING 审中-公开
标题翻译：基于规则的数据正规化利用多重分类
公开(公告)号：US20160188654A1
公开(公告)日：2016-06-30
申请号：US14582510
申请日：2014-12-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Pao-Po Hou , Derek C. Tao , Liang-Yu Chen , Shaojie Xu , Kuoyuan Hsu
IPC分类号： G06F17/30
CPC分类号： G06F17/30958
摘要： Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.
摘要翻译：公开了用于有效检索相邻测量值以便能够快速执行基于规则的纠错的方法和系统。一方面，公开了一种使用多键分类的数据归一化方法。在一些实施例中，该方法包括由数据组织引擎接收包括对应的相邻数据的一组未校正的数据。在各种实施例中，数据组织引擎通过构造有向非循环图（DAG）来组织未校正的数据，其中DAG包括多个节点。在一些实施例中，数据组织引擎可以遍历多个节点以检索对应的相邻数据。在检索相邻数据时，基于规则的校正引擎可以利用检索到的对应的相邻数据来校正未校正的数据。

4. 发明授权

US10176282B2 Timing delay characterization method, memory compiler and computer program product 有权
公开(公告)号：US10176282B2
公开(公告)日：2019-01-08
申请号：US14638444
申请日：2015-03-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shaojie Xu , Yukit Tang , Pao-Po Hou , Derek C. Tao , Annie-Li-Keow Lum
IPC分类号： G06F17/50
摘要： A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

5. 发明授权

US09576622B2 Reading data from a memory cell 有权
标题翻译：从存储单元读取数据
公开(公告)号：US09576622B2
公开(公告)日：2017-02-21
申请号：US14163277
申请日：2014-01-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Annie-Li-Keow Lum , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C11/21 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/419
CPC分类号： G11C7/12 , G11C7/18 , G11C11/412 , G11C11/419
摘要： In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.
摘要翻译：响应于对存储单元的数据线进行第一电压方向的存储单元的写入操作，使数据线具有与第一电压方向相反的第二电压方向。

6. 发明授权

US08907428B2 Cell circuits and layouts used in write tracking circuits and read tracking circuits 有权
标题翻译：写跟踪电路和读跟踪电路中使用的单元电路和布局
公开(公告)号：US08907428B2
公开(公告)日：2014-12-09
申请号：US13687366
申请日：2012-11-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jacklyn Chang , Derek C. Tao , Kuoyuan (Peter) Hsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , G11C11/419 , H01L27/11
CPC分类号： G11C11/419 , G11C11/412 , H01L27/1104 , H01L27/1116
摘要： A circuit includes a first transistor and a second transistor of a first type, a first transistor, a second transistor, a third transistor, and a fourth transistor of a second type. The first and second transistors of the first type, and the first transistor and the second transistor of the second type form a cross latch having a first node and a second node. A first terminal of the third transistor of the second type is coupled with the first node. A first terminal of the fourth transistor of the second type is coupled with the second node. At least one of a second terminal of the third transistor of the second type or a second terminal of the fourth transistor of the second type is configured to receive a signal sufficient to turn off the third transistor or the fourth transistor that is not directly from a power source.
摘要翻译：电路包括第一类型的第一晶体管和第二晶体管，第一类型的第一晶体管和第二晶体管，第一晶体管，第二晶体管，第三晶体管和第四晶体管。第一类型的第一和第二晶体管以及第二类型的第一晶体管和第二晶体管形成具有第一节点和第二节点的交叉锁存器。第二类型的第三晶体管的第一端子与第一节点耦合。第二类型的第四晶体管的第一端子与第二节点耦合。第二类型的第三晶体管的第二端子或第二类型的第四晶体管的第二端子中的至少一个被配置为接收足以将不直接从第一晶体管或第二晶体管截止的第三晶体管或第四晶体管截止的信号能量源。

7. 发明授权

US09449681B2 Pre-charging a data line 有权
标题翻译：预充电数据线
公开(公告)号：US09449681B2
公开(公告)日：2016-09-20
申请号：US14746923
申请日：2015-06-23
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Annie-Li-Keow Lum , Derek C. Tao
IPC分类号： G11C7/12 , G11C11/419 , G11C7/10
CPC分类号： G11C11/419 , G11C7/1048 , G11C7/12
摘要： A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal.
摘要翻译：电路包括信号发生电路，该信号产生电路基于与信号发生电路相关联的一列存储单元的时钟信号和列选择信号产生预充电信号。预充电信号的第一状态取决于列选择信号的第一状态，列选择信号的第一状态对应于存储单元列的选择。电路还包括与信号发生电路相关联的充电电路和耦合到充电电路的第一数据线。充电电路响应于预充电信号的第一状态对第一数据线进行充电，并且允许第一数据线响应于预充电信号的第二状态而浮动。

8. 发明授权

US09368443B1 Memory metal scheme 有权
标题翻译：记忆金属方案
公开(公告)号：US09368443B1
公开(公告)日：2016-06-14
申请号：US14600666
申请日：2015-01-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Jacklyn Chang , Kuoyuan (Peter) Hsu , Yukit Tang
IPC分类号： G11C5/02 , G11C5/06 , H01L23/50 , H01L23/48 , H01L21/768 , H01L27/06
CPC分类号： H01L27/11 , G11C5/02 , G11C5/06 , G11C11/418 , G11C11/419 , G11C2213/71 , H01L23/50 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/0688 , H01L27/1116 , H01L2224/73265
摘要： A memory includes a plurality of memory cells. A first line is over the plurality of memory cells. The first line in a first layout section includes a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A second line is over the plurality of memory cells. The second line in the first layout section includes the first metal layer and a third metal layer. The third metal layer is over the second metal layer The first line is electrically isolated from the second line. The first line and the second line extend in a same direction.
摘要翻译：存储器包括多个存储单元。第一行在多个存储单元之上。第一布局部分的第一行包括第一金属层和第二金属层。第二金属层在第一金属层之上。第二行在多个存储单元之上。第一布局部分的第二行包括第一金属层和第三金属层。第三金属层在第二金属层之上第一线与第二线电隔离。第一行和第二行沿相同方向延伸。

9. 发明授权

US09343125B2 Memory macro with a voltage keeper 有权
标题翻译：具有电压保持器的存储器宏
公开(公告)号：US09343125B2
公开(公告)日：2016-05-17
申请号：US14620769
申请日：2015-02-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Derek C. Tao , Bing Wang , Allen Fan , Yukit Tang , Annie-Li-Keow Lum , Kuoyuan Hsu
IPC分类号： G11C7/10 , G11C7/12 , G11C8/00 , G11C7/18 , G11C11/419
CPC分类号： G11C7/12 , G11C7/18 , G11C8/00 , G11C11/419
摘要： A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.
摘要翻译：存储器宏包括第一数据线，第二数据线，第一开关和电压保持器。第一开关配置在第一数据线和第二数据线之间。电压保持器电耦合到第二数据线。电压保持器被配置为在第一开关期间响应于第二数据线处的电压电平来控制第二数据线处的电压电平将第二数据线电耦合到第一数据线。

10. 发明授权

US09019753B2 Two-port SRAM write tracking scheme 有权
标题翻译：双端口SRAM写入跟踪方案
公开(公告)号：US09019753B2
公开(公告)日：2015-04-28
申请号：US14094833
申请日：2013-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Bing Wang , Kuoyuan (Peter) Hsu , Derek C. Tao
IPC分类号： G11C11/419 , G11C11/413
CPC分类号： G11C11/419 , G11C11/413
摘要： A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit.
摘要翻译：写跟踪控制电路包括输入节点和被配置为对连接到至少两个存储器单元的字位线进行预充电的第一晶体管。写跟踪控制电路还包括第二晶体管，其被配置为对连接到所述至少两个存储单元的读位线进行预充电。写跟踪控制电路还包括在输入节点和第一晶体管之间的第一延迟电路，第一延迟电路被配置为引入第一延迟时间，其中第一晶体管的栅极连接到第一延迟电路。写跟踪控制电路还包括在输入节点和第二晶体管之间的第二延迟电路，第二延迟电路被配置为引入不同于第一延迟时间的第二延迟时间，其中第二晶体管的栅极连接到第二延迟时间延时电路。

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