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1. 发明授权

US09576622B2 Reading data from a memory cell 有权
标题翻译：从存储单元读取数据
公开(公告)号：US09576622B2
公开(公告)日：2017-02-21
申请号：US14163277
申请日：2014-01-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Annie-Li-Keow Lum , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C11/21 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/419
CPC分类号： G11C7/12 , G11C7/18 , G11C11/412 , G11C11/419
摘要： In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.
摘要翻译：响应于对存储单元的数据线进行第一电压方向的存储单元的写入操作，使数据线具有与第一电压方向相反的第二电压方向。

2. 发明授权

US09412438B2 Writing data to a memory cell 有权
标题翻译：将数据写入存储单元
公开(公告)号：US09412438B2
公开(公告)日：2016-08-09
申请号：US14163025
申请日：2014-01-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kai Fan , Kuoyuan (Peter) Hsu , Bing Wang , Sung-Chieh Lin
IPC分类号： G11C11/00 , G11C11/419
CPC分类号： G11C11/419
摘要： A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.
摘要翻译：电路包括第一晶体管，电容元件，第二晶体管和数据线。第一晶体管具有阈值电压值。第一晶体管的第一端子与电容部件的第一端子和第二晶体管的第二端子耦合。第一晶体管的第二端子被配置为接收第二端电压值。第一晶体管的第三端被配置为接收第三端电压值。第二晶体管的第一端与数据线耦合。第二晶体管的第三端被配置为接收第二晶体管控制信号。第一晶体管被配置为导通和截止，以将数据线保持在数据线电压值。

3. 发明授权

US09218857B2 Method of memory with regulated ground nodes 有权
标题翻译：具有调节地面节点的记忆方法
公开(公告)号：US09218857B2
公开(公告)日：2015-12-22
申请号：US14051682
申请日：2013-10-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuoyuan (Peter) Hsu , Yukit Tang , Derek Tao , Young Seog Kim
IPC分类号： G11C11/40 , G11C7/00 , G11C11/413
CPC分类号： G11C11/419 , G11C7/00 , G11C11/413 , H01L27/11
摘要： A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.
摘要翻译：从存储器阵列的被访问部分的访问列的访问存储器单元读取数据的方法包括在所访问的部分中将至少三个电压源的第一电压源电耦合到相应的列内部接地节点访问列; 并将第一电压源电耦合到未访问的列的相应列内部接地节点。存储器阵列具有至少一个段，所述至少一个段具有至少一个区段，并且每个区段具有至少一个区段。每列具有至少三个开关和列内部接地节点，其能够通过至少三个开关中的相应一个电耦合到至少三个电压源。

4. 发明授权

US08907428B2 Cell circuits and layouts used in write tracking circuits and read tracking circuits 有权
标题翻译：写跟踪电路和读跟踪电路中使用的单元电路和布局
公开(公告)号：US08907428B2
公开(公告)日：2014-12-09
申请号：US13687366
申请日：2012-11-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jacklyn Chang , Derek C. Tao , Kuoyuan (Peter) Hsu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , G11C11/419 , H01L27/11
CPC分类号： G11C11/419 , G11C11/412 , H01L27/1104 , H01L27/1116
摘要： A circuit includes a first transistor and a second transistor of a first type, a first transistor, a second transistor, a third transistor, and a fourth transistor of a second type. The first and second transistors of the first type, and the first transistor and the second transistor of the second type form a cross latch having a first node and a second node. A first terminal of the third transistor of the second type is coupled with the first node. A first terminal of the fourth transistor of the second type is coupled with the second node. At least one of a second terminal of the third transistor of the second type or a second terminal of the fourth transistor of the second type is configured to receive a signal sufficient to turn off the third transistor or the fourth transistor that is not directly from a power source.
摘要翻译：电路包括第一类型的第一晶体管和第二晶体管，第一类型的第一晶体管和第二晶体管，第一晶体管，第二晶体管，第三晶体管和第四晶体管。第一类型的第一和第二晶体管以及第二类型的第一晶体管和第二晶体管形成具有第一节点和第二节点的交叉锁存器。第二类型的第三晶体管的第一端子与第一节点耦合。第二类型的第四晶体管的第一端子与第二节点耦合。第二类型的第三晶体管的第二端子或第二类型的第四晶体管的第二端子中的至少一个被配置为接收足以将不直接从第一晶体管或第二晶体管截止的第三晶体管或第四晶体管截止的信号能量源。

5. 发明授权

US09978446B2 Memory with regulated ground nodes and method of retaining data therein 有权
公开(公告)号：US09978446B2
公开(公告)日：2018-05-22
申请号：US15378821
申请日：2016-12-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuoyuan (Peter) Hsu , Yukit Tang , Derek Tao , Young Seog Kim
IPC分类号： G11C11/40 , G11C11/419 , G11C11/413 , G11C7/00 , H01L27/11
CPC分类号： G11C11/419 , G11C7/00 , G11C11/413 , H01L27/11
摘要： A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.

6. 发明授权

US09779801B2 Method and control circuit for memory macro 有权
公开(公告)号：US09779801B2
公开(公告)日：2017-10-03
申请号：US14598272
申请日：2015-01-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Annie-Li-Keow Lum
IPC分类号： G11C8/16 , G11C11/419 , G11C7/22
CPC分类号： G11C11/419 , G11C7/227 , G11C8/16
摘要： A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.

7. 发明授权

US09449888B2 Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same 有权
标题翻译：集成电路结构解决深井等离子体充电问题及其形成方法
公开(公告)号：US09449888B2
公开(公告)日：2016-09-20
申请号：US14594259
申请日：2015-01-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/263 , H01L29/66 , H01L27/06
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.
摘要翻译：形成集成电路的方法包括在衬底中形成深n阱（DNW），以及在DNW中形成PMOS晶体管。该方法还包括在衬底中形成NMOS晶体管并在DNW外部形成反向偏置二极管。该方法还包括在PMOS晶体管的漏极和NMOS晶体管的栅极结构之间形成电路径。耗散装置也连接到电气路径。

8. 发明授权

US09324393B2 Tracking mechanisms 有权
标题翻译：跟踪机制
公开(公告)号：US09324393B2
公开(公告)日：2016-04-26
申请号：US14679375
申请日：2015-04-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/00 , G11C7/18 , G11C7/22 , G11C7/10 , G11C8/18 , G11C11/419 , G11C11/4076
CPC分类号： G11C7/18 , G11C7/1051 , G11C7/1078 , G11C7/22 , G11C7/227 , G11C8/18 , G11C11/4076 , G11C11/419
摘要： A tracking circuit in a memory macro includes a data line, a tracking cell electrically coupled with the data line, a logical gate, a feedback transistor, and a plurality of pulling devices. The logical gate has an input terminal and an output terminal. The input terminal of the logical gate is electrically coupled with the data line. The feedback transistor has a first terminal, a second terminal, and a gate terminal. The first terminal of the feedback transistor is electrically coupled with the data line, and the gate terminal of the feedback transistor is electrically coupled with the output terminal of the logical gate. The plurality of pulling devices is configured to pull the second terminal of the feedback transistor toward a first voltage.
摘要翻译：存储器宏中的跟踪电路包括数据线，与数据线电耦合的跟踪单元，逻辑门，反馈晶体管和多个牵引装置。逻辑门具有输入端和输出端。逻辑门的输入端与数据线电耦合。反馈晶体管具有第一端子，第二端子和栅极端子。反馈晶体管的第一端与数据线电耦合，并且反馈晶体管的栅极端与逻辑门的输出端电耦合。多个牵引装置被配置为将反馈晶体管的第二端子拉向第一电压。

9. 发明授权

US09966378B2 Integrated circuit structure 有权
公开(公告)号：US09966378B2
公开(公告)日：2018-05-08
申请号：US15262574
申请日：2016-09-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/263 , H01L29/66 , H01L27/06
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.

10. 发明授权

US09887186B2 Memory circuit, layout of memory circuit, and method of forming layout 有权
公开(公告)号：US09887186B2
公开(公告)日：2018-02-06
申请号：US14610158
申请日：2015-01-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Jacklyn Chang , Kuoyuan (Peter) Hsu
IPC分类号： H01L27/02 , H01L27/088 , H01L23/522 , H01L23/528 , H01L27/105 , G06F17/50 , H01L27/112
CPC分类号： H01L27/0207 , G06F17/5072 , H01L23/5226 , H01L23/528 , H01L27/11226
摘要： A memory circuit includes a first active structure extending along a first direction, a second active structure extending along the first direction, a first conductive structure extending along a second direction, and a lowest via plug layer over the first conductive structure. The first active structure has a shared source portion corresponding to a source node of a first memory cell of the memory circuit and a source node of a second memory cell of the memory circuit. The second active structure has a shared source portion corresponding to a source node of a third memory cell of the memory circuit and a source node of a fourth memory cell of the memory circuit. The first conductive structure electrically connects the shared source portion of the first active structure with the shared source portion of the second active structure.

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