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1. 发明授权

US09978446B2 Memory with regulated ground nodes and method of retaining data therein 有权
公开(公告)号：US09978446B2
公开(公告)日：2018-05-22
申请号：US15378821
申请日：2016-12-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuoyuan (Peter) Hsu , Yukit Tang , Derek Tao , Young Seog Kim
IPC分类号： G11C11/40 , G11C11/419 , G11C11/413 , G11C7/00 , H01L27/11
CPC分类号： G11C11/419 , G11C7/00 , G11C11/413 , H01L27/11
摘要： A memory device includes: memory cells arranged in rows and columns; and regulated ground circuits corresponding to the columns. Each regulated ground circuit includes: a column ground node; at least three low-side voltage sources; at least three switches, each of the at least three switches being coupled between the column ground node and a corresponding one of the at least three voltage sources; and each of the at least three switches being controlled by a corresponding one of different control signals; Each memory cell includes: a high-side voltage source; an internal ground node coupled to the column ground node; and a cross latch having output and output_bar nodes. The cross latch is coupled between the high-side voltage source and the internal ground node, and is configured to selectively connect the output and output_bar nodes to corresponding bit and bit_bar lines.

2. 发明授权

US09818752B2 Memory metal scheme 有权
公开(公告)号：US09818752B2
公开(公告)日：2017-11-14
申请号：US15153872
申请日：2016-05-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Jacklyn Chang , Kuoyuan (Peter) Hsu , Yukit Tang
IPC分类号： G11C5/02 , G11C5/06 , H01L27/11 , H01L23/50 , G11C11/418 , G11C11/419 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/06
CPC分类号： H01L27/11 , G11C5/02 , G11C5/06 , G11C11/418 , G11C11/419 , G11C2213/71 , H01L23/50 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/0688 , H01L27/1116 , H01L2224/73265
摘要： A method of fabricating a memory includes forming a first portion of a first line in a first metal layer, forming a first portion of a second line in the first metal layer, forming a second portion of the first line in a second metal layer, and forming a second portion of the second line in a third metal layer. The first line is over a plurality of memory cells. The second line is over the plurality of memory cells, the first line is electrically isolated from the second line, and the first line and the second line extend in a same direction. The second metal layer is over the first metal layer. The third metal layer is over the second metal layer and the third metal layer is electrically isolated from the first line.

3. 发明授权

US09298875B2 Semiconductor circuit design method, memory compiler and computer program product 有权
标题翻译：半导体电路设计方法，内存编译器和计算机程序产品
公开(公告)号：US09298875B2
公开(公告)日：2016-03-29
申请号：US14567383
申请日：2014-12-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shaojie Xu , Yukit Tang , Pao-Po Hou , Derek C. Tao , Annie-Li-Keow Lum
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5036 , G06F2217/82
摘要： A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.
摘要翻译：设计半导体电路的方法包括生成半导体电路的模型。该模型包括对应于半导体电路的第一块的功能区域和对应于半导体电路的第二块的加载区域，其中第一块通过信号线连接到第二块。该方法还包括在功能区域中提取信号线的寄生参数和第一块的装置。该方法还包括在加载区域中提取信号线的寄生参数，而不提取第二块的装置的寄生参数。

4. 发明授权

US08817568B2 Dual rail memory 有权
标题翻译：双轨内存
公开(公告)号：US08817568B2
公开(公告)日：2014-08-26
申请号：US13646238
申请日：2012-10-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first voltage circuit coupled to internal first nodes of memory cells in the one of the plurality of columns and a second voltage circuit coupled to internal second nodes of the memory cells in the one of the plurality of columns. The first voltage circuit is configured to provide one of a first supply voltage and a second supply voltage lower than the first supply voltage to the internal first nodes. The second voltage circuit is configured to provide one of a first reference voltage and a second reference voltage higher than the first reference voltage to the internal second nodes.
摘要翻译：存储器阵列包括以多行和多列布置的多个存储单元。多列的列包括耦合到多列中的一列的存储器单元的内部第一节点的第一电压电路和耦合到多列中的一列的存储单元的内部第二节点的第二电压电路。第一电压电路被配置为向内部第一节点提供低于第一电源电压的第一电源电压和第二电源电压中的一个。第二电压电路被配置为向内部第二节点提供高于第一参考电压的第一参考电压和第二参考电压之一。

5. 发明授权

US10176282B2 Timing delay characterization method, memory compiler and computer program product 有权
公开(公告)号：US10176282B2
公开(公告)日：2019-01-08
申请号：US14638444
申请日：2015-03-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shaojie Xu , Yukit Tang , Pao-Po Hou , Derek C. Tao , Annie-Li-Keow Lum
IPC分类号： G06F17/50
摘要： A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

6. 发明授权

US09576622B2 Reading data from a memory cell 有权
标题翻译：从存储单元读取数据
公开(公告)号：US09576622B2
公开(公告)日：2017-02-21
申请号：US14163277
申请日：2014-01-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Annie-Li-Keow Lum , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C11/21 , G11C7/12 , G11C7/18 , G11C11/412 , G11C11/419
CPC分类号： G11C7/12 , G11C7/18 , G11C11/412 , G11C11/419
摘要： In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.
摘要翻译：响应于对存储单元的数据线进行第一电压方向的存储单元的写入操作，使数据线具有与第一电压方向相反的第二电压方向。

7. 发明授权

US09218857B2 Method of memory with regulated ground nodes 有权
标题翻译：具有调节地面节点的记忆方法
公开(公告)号：US09218857B2
公开(公告)日：2015-12-22
申请号：US14051682
申请日：2013-10-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuoyuan (Peter) Hsu , Yukit Tang , Derek Tao , Young Seog Kim
IPC分类号： G11C11/40 , G11C7/00 , G11C11/413
CPC分类号： G11C11/419 , G11C7/00 , G11C11/413 , H01L27/11
摘要： A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.
摘要翻译：从存储器阵列的被访问部分的访问列的访问存储器单元读取数据的方法包括在所访问的部分中将至少三个电压源的第一电压源电耦合到相应的列内部接地节点访问列; 并将第一电压源电耦合到未访问的列的相应列内部接地节点。存储器阵列具有至少一个段，所述至少一个段具有至少一个区段，并且每个区段具有至少一个区段。每列具有至少三个开关和列内部接地节点，其能够通过至少三个开关中的相应一个电耦合到至少三个电压源。

8. 发明授权

US10424587B2 Memory metal scheme 有权
公开(公告)号：US10424587B2
公开(公告)日：2019-09-24
申请号：US15791601
申请日：2017-10-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Jacklyn Chang , Kuoyuan (Peter) Hsu , Yukit Tang
IPC分类号： H01L23/528 , H01L23/535 , G11C5/06 , H01L27/11 , H01L23/50 , G11C11/418 , G11C11/419 , H01L23/522 , H01L27/02 , H01L27/06 , G11C5/02
摘要： A method of fabricating a memory array includes designing first layout sections in a row direction, each first layout section including first and second control lines in a first metal layer, and an upper conductive line in a third metal layer. A lower conductive line in a second metal layer is coupled to the first control line and the first control line is isolated from the second control line. A second layout section is inserted at every N-th first layout section, N being a positive integer equal to or greater than 2. The second layout section includes the first control line, the second control line and a lower conductive line in the second metal layer coupled to the second control line and to an upper conductive line in the third metal layer. The lower conductive lines in the first and second layout sections are isolated from each other.

9. 发明授权

US09478269B2 Tracking mechanisms 有权
标题翻译：跟踪机制
公开(公告)号：US09478269B2
公开(公告)日：2016-10-25
申请号：US14541687
申请日：2014-11-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Derek C. Tao , Annie-Li-Keow Lum , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/10 , G11C7/22 , G11C11/419
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要： A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated.
摘要翻译：存储器宏包括对应于多个跟踪电路的多个段。因此，多个段的每个段对应于多个跟踪电路中的一个跟踪电路。响应于片段的存储器单元的读取操作，对应于片段的跟踪电路被配置为生成跟踪信号的边缘，基于该边缘生成与存储器单元相关联的单元信号的第一边缘。

10. 发明授权

US09418717B2 Tracking mechanism for writing to a memory cell 有权
标题翻译：用于写入存储单元的跟踪机制
公开(公告)号：US09418717B2
公开(公告)日：2016-08-16
申请号：US14602805
申请日：2015-01-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
IPC分类号： G11C7/22 , G11C11/419 , G11C7/12
CPC分类号： G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要： A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.
摘要翻译：电路包括写驱动器，数据电路，存储单元，跟踪写缓冲器，跟踪写驱动器和跟踪单元。电路被配置为：在基于时钟信号的存储单元的写入操作期间，写入驱动器电路被配置为产生写入控制信号以控制存储器单元; 数据电路被配置为向存储器单元提供写入数据; 跟踪写缓冲器被配置为产生跟踪写入控制信号; 并且跟踪写入驱动器被配置为产生要传送到跟踪单元的跟踪写入数据信号。跟踪单元被配置为响应于跟踪写控制信号，基于跟踪写数据信号的逻辑值来调整跟踪单元的第一节点处的信号。

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